WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 138
WG82577LM S LGWR
Manufacturer Part Number
WG82577LM S LGWR
Description
Manufacturer
Intel
Datasheet
1.WG82577LM_S_LGWR.pdf
(195 pages)
Specifications of WG82577LM S LGWR
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 138 of 195
- Download datasheet (2Mb)
10.2.1.1.12 Extended Configuration Size - EXTCNF_SIZE (0x00F08; RW)
10.2.1.1.13 PHY Control Register - PHY_CTRL (0x00F10; RW)
131
This register is initialized to a hardware default at LAN_RST# reset.
31:24
23:16
15:0
31:29
28:25
24
23
22:20
19:17
16:7
6
5:4
3
2
1
0
Bit
Bit
RO
RW/SN
RW/SN
RO
RO
RO
RO
RW
RW
RO
RW/SN
RO
RW/SN
RW/SN
RW/SN
RW/SN
Type
Type
82577 GbE PHY—Intel
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x2
0x0
0b
00b
1b
1b
0b
0b
Reset
Reset
Reserved.
Extended LCD Length. Size (in Dwords) of the extended PHY configuration
area loaded from Extended Configuration word 2 in the NVM. If an
extended configuration area is disabled by the LCD Write Enable field in
word 0x14 in the NVM, this length must be set to zero.
Reserved
Reserved
SKU Read Data. These four bits contain the SKU value read from the
82577 SKU register. Using these bits, the SKU mechanism determines the
Device ID.
Reserved.
SKU done. This bit indicates the termination of SKU read.
Reserved.
Reserved.
Reserved
Global GbE Disable. Prevents the 82577 from auto negotiating 1000 Mb/s
link in all power states (including D0a). This bit is initialized by word 0x17,
bit 14 in the NVM.
Reserved.
GbE Disable at Non D0a. Prevents the 82577 from auto negotiating
1000 Mb/s link in all power states except D0a (DR, D0u and D3). Bit is
initialized by word 0x17, bit 11 in the NVM. This bit must be set since GbE
is not supported in Sx by the platform.
LPLU in Non D0a. Enables the 82577 to negotiate for slowest possible link
(reverse auto negotiate) in all power states except D0a (DR, D0u and D3).
This bit is initialized by word 0x17, bit 10 in the NVM.
LPLU in D0a. Enables the 82577 to negotiate for the slowest possible link
(reverse auto negotiate) in all power states (including D0a). This bit
overrides the LPLU in non-D0abit. This bit is initialized by word 0x17, bit 9
in the NVM.
Reserved.
®
5 Series Express Chipset MAC Programming Interface
Description
Description
Related parts for WG82577LM S LGWR
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
Intel
Datasheet:
Part Number:
Description:
Microprocessor: Intel Celeron M Processor 320 and Ultra Low Voltage Intel Celeron M Processor at 600MHz
Manufacturer:
Intel Corporation
Part Number:
Description:
Intel 82550 Fast Ethernet Multifunction PCI/CardBus Controller
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 32 Mbit. Access speed 120 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 32 Mbit. Access speed 120 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 64 Mbit. Access speed 150 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 32 Mbit. Access speed 100 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
DA28F640J5A-1505 Volt Intel StrataFlash Memory
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
5 Volt Intel StrataFlash?? Memory
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
5 Volt Intel StrataFlash?? Memory
Manufacturer:
Intel Corporation
Part Number:
Description:
Intel 6300ESB I/O Controller Hub
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel 82801DB I/O Controller Hub (ICH4), Pb-Free SLI
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel 82801FB I/O Controller Hub (ICH6)
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel Strataflash Memory28F128J3 28F640J3 28F320J3
Manufacturer:
Intel Corporation
Datasheet: