LSM303DLM STMicroelectronics, LSM303DLM Datasheet
LSM303DLM
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LSM303DLM Summary of contents
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... Magnetic and accelerometer parts can be enabled or put into power-down mode separately. The LSM303DLM is available in a plastic land grid array package (LGA), and is guaranteed to operate over an extended temperature range from -40 to +85 °C. Table 1. ...
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... External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 High current wiring effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1.1 7.1.2 7.1.3 8 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/38 2 Sensor inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Linear acceleration digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Magnetic field digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Doc ID 018725 Rev 1 LSM303DLM ...
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... LSM303DLM 9.1 Linear acceleration register description . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.1.8 9.1.9 9.1.10 9.1.11 9.1.12 9.1.13 9.1.14 9.1.15 9.1.16 9.1.17 9.1.18 9.1.19 9.2 Magnetic field sensing register description . . . . . . . . . . . . . . . . . . . . . . . 32 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.2.9 10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11 Revision history ...
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... INT1_CFG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 38. Interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 39. INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 40. INT1_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 41. INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 42. INT1_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 43. INT1_DURATION_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 44. INT2_DURATION_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 45. INT2_CFG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 46. INT2_CFG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 47. Interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 48. INT2_SRC_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4/38 Doc ID 018725 Rev 1 LSM303DLM ...
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... LSM303DLM Table 49. INT2_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 50. INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 51. INT2_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 52. INT2_DURATION_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 53. INT2_DURATION_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 54. CRA_REG_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 55. CRA_REG_M description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 56. Data rate configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 57. CRA_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 58. Gain setting Table 59. MR_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 60. MR_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 61. Magnetic sensor operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 62 ...
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... Block diagram Sensing Block I (a) I (M) 6/38 A/D Sensing Interface converter X+ Y+ CHARGE AMPLIFIER Z+ + MUX - CHARGE Y+ AMPLIFIER Z+ + MUX - INTERRUPT GEN. REFERENCE OFFSET CLOCK CIRCUITS Doc ID 018725 Rev 1 LSM303DLM Control Logic SDA_A SCL_A SDA_M SCL_M INT1 INT2 TRIMMING CIRCUITS BUILT-IN SET/RESET CIRCUITS AM09239V1 ...
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... LSM303DLM 1.2 Pin description Figure 2. Pin connection Table 2. Pin description Pin Name Reserved Connect to GND GND 0 V supply Reserved Connect to GND Linear acceleration signal I SA0_A address (SA0) NC Internally not connected Vdd Power supply Reserved Connect to Vdd Reserved Leave unconnected Reserved Leave unconnected ...
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... Signal interface power supply for I/O pins Reserved Connect to Vdd_IO SCL_A Linear acceleration signal interface I SDA_A Linear acceleration signal interface I INT1 Inertial Interrupt 1 INT2 Inertial Interrupt 2 Reserved Connect to GND Doc ID 018725 Rev 1 LSM303DLM Function 2 C serial clock (SCL serial clock (SCL serial data (SDA) ...
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... LSM303DLM 2 Module specifications 2.1 Sensor characteristics @ Vdd = 2 °C unless otherwise noted Table 3. Sensor characteristics Symbol Parameter Linear acceleration LA_FS measurement range M_FS Magnetic measurement range LA_So Linear acceleration sensitivity M_GN Magnetic gain setting a. The product is factory calibrated at 2.5 V. The operational power supply range is from 2. 3.6 V. ...
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... Max. delta from 25 °C Cross field = 0.5 gauss H applied = ±3 gauss No permitting effect on zero reading Sensitivity starts to degrade. Use S/R pulse to restore sensitivity -40 Test Min. conditions 2.16 1.71 - -40 Doc ID 018725 Rev 1 LSM303DLM (1) Typ. Max. Unit ±0.01 %/°C g ± ±0.5 m /°C %FS/ ±1 gauss ...
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... LSM303DLM 2.3 Communication interface characteristics 2 2.3.1 Sensor inter IC control interface Subject to general operating conditions for Vdd and top. 2 Table slave timing values Symbol Parameter f SCL clock frequency (SCL) t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time ...
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... This is a mechanical shock sensitive device, improper handling can cause permanent damage to the part. This is an ESD sensitive device, improper handling can cause permanent damage to the part. 12/38 Ratings Doc ID 018725 Rev 1 LSM303DLM Maximum value Unit -0.3 to 4.8 V -0.3 to 4.8 V -0.3 to Vdd_IO +0.3 ...
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... The “sleep-to-wakeup” function, in conjunction with low-power mode, allows further reduction of system power consumption and the development of new smart applications. The LSM303DLM may be set to a low-power operating mode, characterized by lower data rate refreshing. In this way, the device, even if sleeping, continues sensing acceleration and generating interrupt requests ...
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... IC interfaces are realized using a CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. The LSM303DLM features two data-ready signals (RDY) which indicate when a new set of measured acceleration data and magnetic data are available, therefore simplifying data synchronization in the digital system that uses the device ...
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... LSM303DLM 6 Application hints Figure 4. LSM303DLM electrical connection - recommended for I Electrical connection Vdd DIRECTIONS OF DETECTABLE MAGNETIC FIELDS DIRECTIONS OF DETECTABLE ACCELERATIONS 6.1 External capacitors The C1 and C2 external capacitors should have a low SR value ceramic type construction. Reservoir capacitor C1 is nominally 4.7 µF in capacitance, with the set/reset capacitor C2 nominally 0.22 µ ...
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... Conductor-generated magnetic fields add to the Earth’s magnetic field, creating errors in compass heading computation. Keep currents that are higher than few millimeters further away from the sensor IC. 16/38 ® , RoHS and “Green” standard. Doc ID 018725 Rev 1 LSM303DLM ...
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... LSM303DLM 7 Digital interfaces The registers embedded inside the LSM303DLM are accessible through two separate I serial interfaces; one for the accelerometer core and the other for the magnetometer core. The two interfaces can be connected together on the PCB. Table 7. Serial interface pin description ...
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... The I C embedded inside the LSM303DLM behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent. Once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted; the 7 LSBs represent the actual register address while the MSB enables address auto- increment. If the MSb of the SUB field is ‘ ...
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... LSM303DLM 7.1.2 Linear acceleration digital interface For linear acceleration, the default (factory) 7-bit slave address is 001100xb. The SDO/SA0 pad can be used to modify the least significant bit of the device address. If the SA0 pad is connected to voltage supply, the LSB is ‘1’ (address 0011001b) otherwise, if the SA0 pad is connected to ground, the LSB value is ‘ ...
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... To minimize communication between the master and magnetic digital interface of LSM303DLM, the address pointer updates automatically without master intervention. This automatic address pointer update has two additional features. First, when address 12 or higher is accessed, the pointer updates to address 00, and secondly, when address 08 is reached, the pointer rolls back to address 03 ...
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... LSM303DLM 8 Register mapping Table 15 provides a listing of the 8-bit registers embedded in the device and the related addresses: Table 15. Register address map Name address Table 12 Reserved (do not modify) Table 12 CTRL_REG1_A Table 12 CTRL_REG2_A Table 12 CTRL_REG3_A Table 12 CTRL_REG4_A Table 12 CTRL_REG5_A Table 12 HP_FILTER_RESET_A Table 12 REFERENCE_A Table 12 ...
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... Their content is automatically restored when the device is powered up. 22/38 Register address Slave Type Hex Doc ID 018725 Rev 1 LSM303DLM Default Comment Binary 00000011 output 00000100 output 00000101 output 00000110 output 00000111 output 00001000 output 00001001 00000000 00001010 01001000 00001011 00110100 00001100 00110011 -- -- Reserved 00001111 00111100 Who Reserved ...
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... LSM303DLM 9 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The register address, made bits, is used to identify them and to write the data through the serial interface. 9.1 Linear acceleration register description 9.1.1 CTRL_REG1_A (20h) Table 16 ...
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... Power mode selection 1 1 Low-power 0 0 Low-power 0 1 Low-power 1 0 Low-power Output data rate [Hz] DR0 ODR 100 0 400 1 1000 HPM0 FDS Table Doc ID 018725 Rev 1 LSM303DLM Output data rate [Hz] ODR Low-pass filter cut-off frequency [Hz 292 780 HPen2 HPen1 HPCF1 22) LP HPCF0 ...
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... LSM303DLM reason, the content of the trimming registers has changed sufficient to use this bit to restore the correct values. When the BOOT bit is set to ‘1’ the content of the internal Flash is copied to the corresponding internal registers and is used to calibrate the device. These values are factory-trimmed and are different for every accelerometer. They permit good device behavior and normally do not have to be modified. At the end of the boot process, the BOOT bit is again set to ‘ ...
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... This feature avoids reading LSB and MSB related to different samples. 26/38 Table 26) Table 26) I1(2)_CFG0 FS1 FS0 Doc ID 018725 Rev 1 LSM303DLM INT 1(2) Pad Interrupt 1 (2) source Interrupt 1 source OR Interrupt 2 source Data ready Boot running ( --- ...
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... LSM303DLM 9.1.5 CTRL_REG5_A (24h) Table 29. CTRL_REG5_A register 0 0 Table 30. CTRL_REG5_A description TurnOn1, Turn-on mode selection for sleep-to-wakeup function. Default value: 00. TurnOn0 TurnOn bits are used for turning on the sleep-to-wakeup function. Table 31. Sleep-to-wakeup configuration TurnOn1 setting the TurnOn [1:0] bits to 11, the “sleep-to-wakeup” function is enabled. When an interrupt event occurs, the device goes into normal mode, increasing the ODR to the value defined in CTRL_REG1_A ...
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... Y-axis acceleration data. The value is expressed as 2’s complement. 9.1.11 OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh) Z-axis acceleration data. The value is expressed as 2’s complement. 9.1.12 INT1_CFG_A (30h) Table 36. INT1_CFG_A register AOI 6D 28/38 YOR XOR ZYXDA ZHIE ZLIE YHIE Doc ID 018725 Rev 1 LSM303DLM ZDA YDA XDA YLIE XHIE XLIE ...
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... LSM303DLM Table 37. INT1_CFG_A description AND/OR combination of interrupt events. Default value: 0 AOI (see 6-direction detection function enable. Default value (see Enable interrupt generation on Z high event. Default value: 0 ZHIE (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event ...
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... The bits set the minimum duration of the Interrupt 2 event to be recognized. Duration steps and maximum values depend on the ODR chosen. 30/38 THS5 THS4 Interrupt 1 threshold. Default value: 000 0000 D5 D4 Duration value. Default value: 000 0000 Doc ID 018725 Rev 1 LSM303DLM THS3 THS2 THS1 THS0 D0 ...
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... LSM303DLM 9.1.16 INT2_CFG_A (34h) Table 45. INT2_CFG_A register AOI 6D Table 46. INT2_CFG_A description AND/OR combination of interrupt events. Default value: 0 AOI (see 6-direction detection function enable. Default value (see Enable interrupt generation on Z high event. Default value: 0 ZHIE (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event ...
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... INT2_SRC_A register if the latched option was chosen. 9.1.18 INT2_THS_A (36h) Table 50. INT2_THS register 0 THS6 Table 51. INT2_THS description THS6 - THS0 9.1.19 INT2_DURATION_A (37h) Table 52. INT2_DURATION_A register 0 D6 32/ THS5 THS4 Interrupt 1 threshold. Default value: 000 0000 D5 D4 Doc ID 018725 Rev 1 LSM303DLM THS3 THS2 THS1 THS0 D0 ...
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... LSM303DLM Table 53. INT2_DURATION_A description The bits set the minimum duration of the Interrupt 2 event to be recognized. Duration time steps and maximum values depend on the ODR chosen. 9.2 Magnetic field sensing register description 9.2.1 CRA_REG_M (00h) Table 54. CRA_REG_M register (1) ( This bit must be set to ‘0’ for correct working of the device. ...
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... Continuous-conversion mode Single-conversion mode Sleep-mode. Device is placed in sleep-mode Sleep-mode. Device is placed in sleep-mode Doc ID 018725 Rev 1 LSM303DLM Gain Z Output range [LSB/Gauss] 980 760 600 0xF800–0x07FF 400 (-2048–2047) 355 295 205 (1) ( MD1 Mode MD0 ...
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... LSM303DLM 9.2.7 SR_REG_M (09h) Table 62. SR register -- -- Table 63. SR register description Data output register lock. Once a new set of measurements is available, this bit LOCK is set when the first magnetic field data register has been read. DRDY Data ready bit. This bit is when a new set of measurements is available. ...
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... Min. Typ. Max. 1 0.785 0.200 4.850 5.000 5.150 4.850 5.000 5.150 1.650 3.300 0.550 0.040 0.100 0.160 0.260 0.300 0.340 0.360 0.400 0.440 0.200 0.050 0.100 Doc ID 018725 Rev 1 LSM303DLM Outline and mechanical data LGA-28 (5x5x1) Land Grid Array Packages 8192208_B ...
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... LSM303DLM 11 Revision history Table 68. Document revision history Date 11-Apr-2011 Revision 1 Initial release. Doc ID 018725 Rev 1 Revision history Changes 37/38 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 38/38 Please Read Carefully: © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 018725 Rev 1 LSM303DLM ...