MT48LC16M16A2P-75:DTR Micron Technology Inc, MT48LC16M16A2P-75:DTR Datasheet - Page 58
MT48LC16M16A2P-75:DTR
Manufacturer Part Number
MT48LC16M16A2P-75:DTR
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC16M16A2P-75DTR.pdf
(87 pages)
Specifications of MT48LC16M16A2P-75:DTR
Lead Free Status / Rohs Status
Compliant
- Current page: 58 of 87
- Download datasheet (4Mb)
Figure 28: READ Continuous Page Burst
Command
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
BA0, BA1
Address
DQM
CKE
A10
CLK
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
Row
Row
Bank
T0
t CKH
t CMH
t AH
t AH
t AH
t RCD
t CL
T1
Note:
NOP
t CH
t CMS
1. For this example, CL = 2.
t CK
Column m
Bank
T2
READ
t CMH
CAS latency
T3
NOP
t LZ
t AC
T4
NOP
D
OUT
t OH
t AC
58
All locations within same row
T5
Full-page burst does not self-terminate.
D
NOP
Can use BURST TERMINATE command.
OUT
t OH
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t AC
Full page completed
T6
NOP
D
OUT
t OH
t AC
(
(
(
(
(
)
)
)
)
)
(
(
(
(
(
(
)
)
)
)
)
)
(
(
(
)
)
)
(
(
(
(
(
(
(
(
(
)
(
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(
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(
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(
(
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)
)
)
)
)
)
)
)
)
(
(
(
(
)
(
)
(
)
256Mb: x4, x8, x16 SDRAM
)
)
)
Tn + 1
NOP
D
OUT
t OH
t AC
© 1999 Micron Technology, Inc. All rights reserved.
BURST TERM
Tn + 2
READ Operation
D
OUT
t OH
t AC
Tn + 3
NOP
D
OUT
t OH
t HZ
Don’t Care
Undefined
Tn + 4
NOP
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