ADL5330ACPZ-WP Analog Devices Inc, ADL5330ACPZ-WP Datasheet

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ADL5330ACPZ-WP

Manufacturer Part Number
ADL5330ACPZ-WP
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADL5330ACPZ-WP

Number Of Channels
1
Supply Current
215(Typ)@5VmA
Frequency (max)
3GHz
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.25V
Power Dissipation
1.1W
Package Type
LFCSP EP
Mounting
Surface Mount
Pin Count
24
Noise Figure (typ)
14.7@2700MHzdB
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
FEATURES
Voltage-controlled amplifier/attenuator
Operating frequency 10 MHz to 3 GHz
Optimized for controlling output power
High linearity: OIP3 31 dBm @ 900 MHz
Output noise floor: −150 dBm/Hz @ 900 MHz
50 Ω input and output impedances
Single-ended or differential operation
Wide gain-control range: −34 dB to +22 dB @ 900 MHz
Linear-in-dB gain control function, 20 mV/dB
Single-supply 4.75 V to 5.25 V
APPLICATIONS
Transmit and receive power control at RF and IF
GENERAL DESCRIPTION
The ADL5330 is a high performance, voltage-controlled
variable gain amplifier/attenuator for use in applications with
frequencies up to 3 GHz. The balanced structure of the signal
path minimizes distortion while it also reduces the risk of
spurious feed-forward at low gains and high frequencies caused
by parasitic coupling. While operation between a balanced
source and load is recommended, a single-sided input is
internally converted to differential form.
The input impedance is 50 Ω from INHI to INLO. The outputs
are usually coupled into a 50 Ω grounded load via a 1:1 balun. A
single supply of 4.75 V to 5.25 V is required.
The 50 Ω input system converts the applied voltage to a pair of
differential currents with high linearity and good common
rejection even when driven by a single-sided source. The signal
currents are then applied to a proprietary voltage-controlled
attenuator providing precise definition of the overall gain under
the control of the linear-in-dB interface. The GAIN pin accepts
a voltage from 0 V at minimum gain to 1.4 V at full gain with a
20 mV/dB scaling factor.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
The output of the high accuracy wideband attenuator is applied
to a differential transimpedance output stage. The output stage
sets the 50 Ω differential output impedances and drives
Pin OPHI and Pin OPLO. The ADL5330 has a power-down
function. It can be powered down by a Logic LO input on the
ENBL pin. The current consumption in power-down mode is
250 μA.
The ADL5330 is fabricated on an ADI proprietary high
performance, complementary bipolar IC process. The ADL5330
is available in a 24-lead (4 mm × 4 mm), Pb-free LFCSP_VQ
package and is specified for operation from ambient
temperatures of −40°C to +85°C. An evaluation board is also
available.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
RFIN
VREF
COM1
INHI
INLO
COM1
VPS1
GAIN
VPS1
60 dB Gain Control Range
10 MHz to 3 GHz VGA with
FUNCTIONAL BLOCK DIAGRAM
CONTROL
STAGE
INPUT
GAIN
VREF
ENBL VPS2
BIAS
AND
IPBS
GM
© 2005 Analog Devices, Inc. All rights reserved.
OPBS
COM1
VPS2
Figure 1.
COM2
VPS2
STAGE
(TZ)
O/P
COM2
VPS2
COM2
COM2
VPS2
OPLO
VPS2
OPHI
ADL5330
www.analog.com
BALUN
RFOUT

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ADL5330ACPZ-WP Summary of contents

Page 1

FEATURES Voltage-controlled amplifier/attenuator Operating frequency 10 MHz to 3 GHz Optimized for controlling output power High linearity: OIP3 31 dBm @ 900 MHz Output noise floor: −150 dBm/Hz @ 900 MHz 50 Ω input and output impedances Single-ended or differential ...

Page 2

ADL5330 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 12 Applications..................................................................................... 13 Basic Connections ...................................................................... 13 RF Input/Output Interface ........................................................ 14 ...

Page 3

SPECIFICATIONS 25°C; M/A-COM ETC1-1-13 1:1 balun at input and output for single-ended 50 Ω match Table 1. Parameter GENERAL Usable Frequency Range Nominal Input Impedance Nominal Output Impedance 100 MHz Gain Control ...

Page 4

ADL5330 Parameter 2200 MHz Gain Control Span Maximum Gain Minimum Gain Gain Flatness vs. Frequency Gain Control Slope Gain Control Intercept Input Compression Point Input Compression Point Output Third-Order Intercept (OIP3) 1 Output Noise Floor Noise Figure 2 Input Return ...

Page 5

ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VPS1, VPS2 RF Input Power at Maximum Gain OPHI, OPLO ENBL GAIN Internal Power Dissipation θ (with Pad Soldered to Board) JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead ...

Page 6

ADL5330 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 3. Pin Function Descriptions Pin No. Mnemonic VPS1, VPS2 COM1 3, 4 INHI, INLO 7 VREF 8 IPBS 9 OPBS 11 GNLO 12, 14, ...

Page 7

TYPICAL PERFORMANCE CHARACTERISTICS –10 +25°C ERROR –20 +85°C GAIN –30 +25°C GAIN –40 –40°C GAIN –50 0 0.2 0.4 0.6 0.8 V (V) GAIN Figure 3. Gain and Gain Law Conformance vs. V over Temperature at ...

Page 8

ADL5330 40 OIP3 30 20 INPUT P1dB 10 0 –10 OUTPUT P1dB –20 –30 –40 0 0.2 0.4 0.6 0.8 V (V) GAIN Figure 9. Input Compression Point, Output Compression Point, OIP3, and Noise Floor vs. V GAIN 40 30 ...

Page 9

OIP3 (–40° OIP3 (+85°C) OIP3 (+25°C) 0 –10 –20 OP1dB (+85°C) –30 –40 OP1dB (+25°C) –50 0 0.2 0.4 0.6 0.8 1.0 V (V) GAIN Figure 15. OP1dB and OIP3 vs. Gain over Temperature at 100 ...

Page 10

ADL5330 18.5 19 19.5 20 20.5 21 21.5 22 22.5 OP1dB (dBm) Figure 21. OP1dB Distribution at 900 MHz at Maximum Gain 9.5 10 ...

Page 11

V = 0.2V GAIN 450MHz 3GHz 180 V = 1.2V GAIN 1.9GHz 210 240 270 Figure 27. Input Impedance (Differential) 0 –5 –10 –15 –20 –25 –30 –35 100 600 1100 1600 2100 FREQUENCY (MHz) Figure 28. ...

Page 12

ADL5330 THEORY OF OPERATION The ADL5330 is a high performance, voltage-controlled variable gain amplifier/attenuator for use in applications with frequencies GHz. This device is intended to serve as an output variable gain amplifier (OVGA) for applications where ...

Page 13

APPLICATIONS BASIC CONNECTIONS Figure 32 shows the basic connections for operating the ADL5330. There are two positive supplies, VPS1 and VPS2, which must be connected to the same potential. Both COM1 and COM2 (common pins) should be connected to a ...

Page 14

ADL5330 RF INPUT/OUTPUT INTERFACE The ADL5330 is primarily designed for differential signals; however, there are several configurations that can be implemented to interface the ADL5330 to single-ended applications. Figure 33 to Figure 35 show three options for differential-to-single-ended interfaces. All ...

Page 15

GAIN CONTROL INPUT When the VGA is enabled, the voltage applied to the GAIN pin sets the gain. The input impedance of the GAIN pin is 1 MΩ. The gain control voltage range is between 0 V and +1.4 V, ...

Page 16

ADL5330 RF INPUT SIGNAL DAC 220pF Figure 37. ADL5330 Operating in an Automatic Gain Control Loop in Combination with the AD8318 Figure 38 shows the transfer function of the output power vs. the VSET voltage over temperature for a 900 ...

Page 17

Figure 40 shows the response of the AGC RF output to a pulse on VSET. As VSET decreases the AGC loop responds with an RF burst. Response time and the amount of signal integration are controlled by ...

Page 18

ADL5330 WCDMA TRANSMIT APPLICATION Figure 43 shows a plot of the output spectrum of the ADL5330 transmitting a single-carrier WCDMA signal (Test Model 1-64 at 2140 MHz). The carrier power output is approximately −9.6 dBm. The gain control voltage is ...

Page 19

CDMA2000 TRANSMIT APPLICATION To test the compliance to the CDMA2000 base station standard, an 880 MHz, three-carrier CDMA2000 test model signal (forward pilot, sync, paging, and six traffic, as per 3GPP2 C.S0010-B, Table 6.5.2.1) was applied to the ADL5330. A ...

Page 20

ADL5330 EVALUATION BOARD Figure 49 shows the schematic of the ADL5330 evaluation board. The silkscreen and layout of the component and circuit sides are shown in Figure 50 through Figure 53. The board is powered by a single-supply in the ...

Page 21

VPS2 COM2 VPS2 GNLO VPS2 COM1 VPS2 OPBS ENBL IPBS GAIN VREF Figure 49. Evaluation Board Schematic Rev Page ADL5330 ...

Page 22

ADL5330 Table 5. Evaluation Board Configuration Options Components Function C10, C13, Power Supply Decoupling. The nominal supply decoupling consists of C14, R2, R4, R5, R6, R12 100 pF and 0.1 μF capacitors at each power ...

Page 23

Figure 50. Component Side Silkscreen Figure 51. Circuit Side Silkscreen Figure 52. Component Side Layout Figure 53. Circuit Side Layout Rev Page ADL5330 ...

Page 24

... ADL5330 OUTLINE DIMENSIONS PIN 1 INDICATOR 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1, 2 ADL5330ACPZ-WP −40°C to +85°C 1 ADL5330ACPZ-REEL7 −40°C to +85°C 1 ADL5330ACPZ-R2 −40°C to +85°C ADL5330-EVAL Pb-free part waffle pack. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...

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