ATMEGA328P-20PU Atmel, ATMEGA328P-20PU Datasheet - Page 67

• Manufacturer Part Number: ATMEGA328P-20PU
• Manufacturer: Atmel

Specifications of ATMEGA328P-20PU

• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SPI/TWI/USART
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Total Internal Ram Size: 2KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 6-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 28
• Package Type: PDIP
• Lead Free Status / Rohs Status: Compliant

12. External Interrupts
12.1
8025K–AVR–10/09
Pin Change Interrupt Timing
The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23..0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23..0 pins
are configured as outputs. This feature provides a way of generating a software interrupt. The
pin change interrupt PCI2 will trigger if any enabled PCINT23..16 pin toggles. The pin change
interrupt PCI1 will trigger if any enabled PCINT14..8 pin toggles. The pin change interrupt PCI0
will trigger if any enabled PCINT7..0 pin toggles. The PCMSK2, PCMSK1 and PCMSK0 Regis-
ters control which pins contribute to the pin change interrupts. Pin change interrupts on
PCINT23..0 are detected asynchronously. This implies that these interrupts can be used for
waking the part also from sleep modes other than Idle mode.
The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is
set up as indicated in the specification for the External Interrupt Control Register A – EICRA.
When the INT0 or INT1 interrupts are enabled and are configured as level triggered, the inter-
rupts will trigger as long as the pin is held low. Note that recognition of falling or rising edge
interrupts on INT0 or INT1 requires the presence of an I/O clock, described in
and their Distribution” on page
nously. This implies that this interrupt can be used for waking the part also from sleep modes
other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in
An example of timing of a pin change interrupt is shown in
Figure 12-1. Timing of pin change interrupts
”System Clock and Clock Options” on page
pcint_setflag
pcint_in_(0)
PCINT(0)
pcint_syn
pin_sync
pin_lat
PCINT(0)
PCIF
clk
clk
LE
pin_lat
26. Low level interrupt on INT0 and INT1 is detected asynchro-
D
Q
pin_sync
PCINT(0) in PCMSK(x)
26.
pcint_in_(0)
0
x
clk
ATmega48P/88P/168P
Figure
pcint_syn
12-1.
pcint_setflag
PCIF
”Clock Systems
67