ATMEGA328P-20PU Atmel, ATMEGA328P-20PU Datasheet - Page 77

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ATMEGA328P-20PU

Manufacturer Part Number
ATMEGA328P-20PU
Description
Manufacturer
Atmel
Datasheet

Specifications of ATMEGA328P-20PU

Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SPI/TWI/USART
Program Memory Type
Flash
Program Memory Size
32KB
Total Internal Ram Size
2KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
6-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
28
Package Type
PDIP
Lead Free Status / Rohs Status
Compliant
13.3
8025K–AVR–10/09
Alternate Port Functions
ing inputs should be avoided to reduce current consumption in all other modes where the digital
inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset. If low power consumption during reset is
important, it is recommended to use an external pull-up or pull-down. Connecting unused pins
directly to V
accidentally configured as an output.
Most port pins have alternate functions in addition to being general digital I/Os.
shows how the port pin control signals from the simplified
ridden by alternate functions. The overriding signals may not be present in all port pins, but the
figure serves as a generic description applicable to all port pins in the AVR microcontroller
family.
Figure 13-5. Alternate Port Functions
Note:
PTOExn:
PUOExn:
PUOVxn:
DDOExn:
DDOVxn:
PVOExn:
PVOVxn:
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP:
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
CC
Pxn PULL-UP OVERRIDE ENABLE
Pxn PULL-UP OVERRIDE VALUE
Pxn DATA DIRECTION OVERRIDE ENABLE
Pxn DATA DIRECTION OVERRIDE VALUE
Pxn PORT VALUE OVERRIDE ENABLE
Pxn PORT VALUE OVERRIDE VALUE
SLEEP CONTROL
Pxn, PORT TOGGLE OVERRIDE ENABLE
or GND is not recommended, since this may cause excessive currents if the pin is
1
0
1
0
1
0
1
0
PUOExn
PUOVxn
DIEOExn
DDOExn
DDOVxn
PVOExn
PVOVxn
DIEOVxn
SLEEP
(1)
PUD:
WDx:
RDx:
RRx:
WRx:
RPx:
WPx:
clk
DIxn:
AIOxn:
SYNCHRONIZER
D
L
I/O
SET
CLR
:
Q
Q
WRITE DDRx
WRITE PORTx
ATmega48P/88P/168P
PULLUP DISABLE
READ DDRx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
D
PINxn
CLR
Q
Q
Figure 13-2 on page 73
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
1
0
clk
PUD
WDx
RRx
DIxn
AIOxn
RDx
RPx
I/O
WRx
PTOExn
WPx
can be over-
Figure 13-5
I/O
,
77

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