ATMEGA328P-20PU Atmel, ATMEGA328P-20PU Datasheet - Page 81

• Manufacturer Part Number: ATMEGA328P-20PU
• Manufacturer: Atmel

Specifications of ATMEGA328P-20PU

• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SPI/TWI/USART
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Total Internal Ram Size: 2KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 6-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 28
• Package Type: PDIP
• Lead Free Status / Rohs Status: Compliant

8025K–AVR–10/09
(one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer
function.
PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source.
• ICP1/CLKO/PCINT0 – Port B, Bit 0
ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1.
CLKO, Divided System Clock: The divided system clock can be output on the PB0 pin. The
divided system clock will be output if the CKOUT Fuse is programmed, regardless of the
PORTB0 and DDB0 settings. It will also be output during reset.
PCINT0: Pin Change Interrupt source 0. The PB0 pin can serve as an external interrupt source.
Table 13-4
signals shown in
tute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 13-4.
Notes:
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
1. INTRC means that one of the internal RC Oscillators are selected (by the CKSEL fuses),
EXTCK means that external clock is selected (by the CKSEL fuses)
and
PB7/XTAL2/
TOSC2/PCINT7
INTRC • EXTCK+
AS2
0
INTRC • EXTCK+
AS2
0
0
0
INTRC • EXTCK +
AS2 + PCINT7 •
PCIE0
(INTRC + EXTCK) •
AS2
PCINT7 INPUT
Oscillator Output
Overriding Signals for Alternate Functions in PB7..PB4
Table 13-5 on page 82
Figure 13-5 on page
(1)
PB6/XTAL1/
TOSC1/PCINT6
INTRC + AS2
0
INTRC + AS2
0
0
0
INTRC + AS2 +
PCINT6 • PCIE0
INTRC • AS2
PCINT6 INPUT
Oscillator/Clock
Input
77. SPI MSTR INPUT and SPI SLAVE OUTPUT consti-
relate the alternate functions of Port B to the overriding
(1)
ATmega48P/88P/168P
PB5/SCK/
PCINT5
SPE • MSTR
PORTB5 • PUD
SPE • MSTR
0
SPE • MSTR
SCK OUTPUT
PCINT5 • PCIE0
1
PCINT5 INPUT
SCK INPUT
–
PB4/MISO/
PCINT4
SPE • MSTR
PORTB4 • PUD
SPE • MSTR
0
SPE • MSTR
SPI SLAVE
OUTPUT
PCINT4 • PCIE0
1
PCINT4 INPUT
SPI MSTR INPUT
–
81