W78E58BP-40 Nuvoton Technology Corporation of America, W78E58BP-40 Datasheet - Page 5

• Manufacturer Part Number: W78E58BP-40
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W78E58BP-40

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4. PIN DESCRIPTION
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
P0.0 − P0.7
P1.0 − P1.7
P2.0 − P2.7
P3.0 − P3.7
P4.0 − P4.3
SYMBOL
XTAL1
XTAL2
PSEN
RST
ALE
V
V
EA
DD
SS
TYPE
I/O D PORT 0: Function is the same as that of standard 8052.
I/O H PORT 1: Function is the same as that of standard 8052.
I/O H
I/O H PORT 3: Function is the same as that of the standard 8052.
I/O H PORT 4: A bi-directional I/O. See details below.
O H
O H
I L
O
I
I
I
I
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
external ROM. The ROM address and data will not be presented on the bus if
the EA pin is high.
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus. When internal ROM access is performed, no PSEN
strobe signal outputs originate from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: Ground potential.
POWER SUPPLY: Supply voltage for operation.
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
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DESCRIPTIONS
W78E58B/W78E058B
Publication Release Date: April 22, 2008
Revision A9