AT17C128-10PU Atmel, AT17C128-10PU Datasheet
AT17C128-10PU
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AT17C128-10PU Summary of contents
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... FPGA devices. The user can select the polarity of the reset function by pro- gramming four EEPROM bytes. These devices also support a write-protection mechanism within its programming mode. The AT17LV series configurators can be programmed with industry-standard pro- grammers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. ® ® ™ ...
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... The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-lead SOIC package is not available for the AT17LV512/010/002 devices possible to use an 8-lead LAP package instead. 2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the AT17LV512/010/002 devices. 3. Refer to the AT17Fxxx datasheet, available on the Atmel web site. 8-lead LAP DATA CLK (1) ...
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Figure 2-4. Notes: Figure 2-5. Note: 2321H–CNFG–03/06 AT17LV65/128/256/512/010/002/040 20-lead PLCC CLK 4 (2) (WP1 ) NC 5 (1) (WP ) RESET/OE 6 (2) (WP2 ) This pin is only available on AT17LV65/128/256 devices. 2. This ...
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Figure 2-6. Notes: Figure 2-7. AT17LV65/128/256/512/010/002/040 4 (1) 20-lead SOIC DATA CLK RESET/ This pinout only applies to AT17LV512/010/002 devices. 2. The ...
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Figure 2-8. Note: 2321H–CNFG–03/06 AT17LV65/128/256/512/010/002/040 44 TQFP (1) (WP1 ) This pin is only available on AT17LV002 ...
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Figure 2-9. Block Diagram SER_EN (2) WP1 (2) WP2 POWER ON RESET Notes: 1. This pin is only available on AT17LV65/128/256 devices. 2. This pin is only available on AT17LV512/010/002 devices. 3. The CEO feature is not available on the ...
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... When RESET/OE is driven High, the configuration EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17LV series configurator held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated ...
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... CE input of the next device in the chain. It will stay Low as long Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until the entire EEPROM is read again. This CEO feature is not available on the AT17LV65 device. AT17LV65/128/256/512/010/002/040 8 and GND is recommended ...
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... FPGA mode pins. In Master mode, the FPGA automatically loads the config- uration program from an external memory. The AT17LV Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode. This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xil- inx applications. 6. Control of Configuration Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and self-explanatory ...
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... Cascading Serial Configuration EEPROMs For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. After the last bit from the first configurator is read, the clock signal to the configurator asserts its CEO output Low and disables its DATA line driver. The second configurator recognizes the Low level on its CE input and enables its DATA output ...
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Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85 °C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground ..............................-0. Supply Voltage (V ) .........................................-0.5V to +7.0V CC Maximum Soldering Temp. (10 sec. ...
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DC Characteristics V = 3.3V ± 10% CC Symbol Description V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage ( Low-level Output Voltage ( High-level Output Voltage (I ...
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AC Waveforms CE RESET/OE CLK T CE DATA 16. AC Waveforms when Cascading RESET/OE CE CLK T DATA T CEO 2321H–CNFG–03/06 AT17LV65/128/256/512/010/002/040 T SCE CAC CDF LAST BIT T OCK OCE T ...
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AC Characteristics V = 3.3V ± 10% CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC T Data Hold from CE, OE, or CLK ...
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AC Characteristics ± 5% Commercial ± 10% Industrial CC CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC ...
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... Thin Plastic Quad Flat 44A Package (TQFP) Plastic Leaded Chip Carrier 44J (PLCC) Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site. 2. Airflow = 0 ft/min. AT17LV65/128/256/512/010/002/040 16 (1) AT17LV65/ AT17LV128/ AT17LV512/ AT17LV256 AT17LV010 θ ...
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... Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 2321H–CNFG–03/06 AT17LV65/128/256/512/010/002/040 AT17LV65A-10PC Size (Bits) Special Pinouts 65 = 65K A = Altera 128 = 128K Blank = Xilinx /Atmel/ Other 256 = 256K 512 = 512K 010 = 1M 002 = 2M 040 = 4M Package Type Package ...
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Ordering Information 22.1 Standard Package Options Memory Size (1) 64-Kbit (1) 128-Kbit (1) 256-Kbit (1) 512-Kbit AT17LV65/128/256/512/010/002/040 18 Ordering Code AT17LV65-10CC AT17LV65-10PC AT17LV65-10NC AT17LV65-10JC AT17LV65-10SC AT17LV65-10CI AT17LV65-10PI AT17LV65-10NI AT17LV65-10JI AT17LV65-10SI AT17LV128-10CC AT17LV128-10PC AT17LV128-10NC AT17LV128-10JC AT17LV128-10SC AT17LV128-10CI AT17LV128-10PI AT17LV128-10NI AT17LV128-10JI ...
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Standard Package Options (Continued) Memory Size (1) 1-Mbit (1) 2-Mbit (1) 4-Mbit Notes: 1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics. 2. The last-time buy is April 11, 2006 for shaded parts. ...
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Green Package Options (Pb/Halide-free/RoHS Compliant) Memory Size (1) 256-Kbit (1) 512-Kbit (1) 1-Mbit (1) 2-Mbit AT17LV002-10TQU (1) 4-Mbit AT17LV040-10TQU Note: 1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics. AT17LV65/128/256/512/010/002/040 20 Ordering Code ...
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Packaging Information 23.1 8CN4 – LAP Marked Pin1 Indentifier E 0.10 mm TYP Bottom View Note: 1. Metal Pad Dimensions. 2325 Orchard Parkway San Jose, CA 95131 R 2321H–CNFG–03/06 AT17LV65/128/256/512/010/002/040 D Top View ...
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PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with ...
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SOIC TOP VIEW e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R ...
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PLCC 1.14(0.045) X 45˚ B 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...
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SOIC Top View e D Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information. 2. Dimension "D" does not include mold Flash, protrusions or gate ...
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TQFP PIN 1 PIN 1 IDENTIFIER e C 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per ...
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PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per ...
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Revision History Revision Level – Release Date H – March 2006 AT17LV65/128/256/512/010/002/040 28 History Added last-time buy for AT17LVXXX-10CC and AT17LVXXX-10CI. 2321H–CNFG–03/06 ...
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