MC68HC711E9FU Freescale Semiconductor, MC68HC711E9FU Datasheet - Page 123

MC68HC711E9FU

Manufacturer Part Number
MC68HC711E9FU
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC711E9FU

Cpu Family
HC11
Device Core Size
8b
Frequency (max)
4MHz
Interface Type
SCI/SPI
Program Memory Type
EPROM
Program Memory Size
12KB
Total Internal Ram Size
512Byte
# I/os (max)
38
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC711E9FU
Manufacturer:
MOT
Quantity:
47
A write collision is normally a slave error because a slave has no control over when a master initiates a
transfer. A master knows when a transfer is in progress, so there is no reason for a master to generate a
write-collision error, although the SPI logic can detect write collisions in both master and slave devices.
The SPI configuration determines the characteristics of a transfer in progress. For a master, a transfer
begins when data is written to SPDR and ends when SPIF is set. For a slave with CPHA equal to 0, a
transfer starts when SS goes low and ends when SS returns high. In this case, SPIF is set at the middle
of the eighth SCK cycle when data is transferred from the shifter to the parallel data register, but the
transfer is still in progress until SS goes high. For a slave with CPHA equal to 1, transfer begins when the
SCK line goes to its active level, which is the edge at the beginning of the first SCK cycle. The transfer
ends in a slave in which CPHA equals 1 when SPIF is set.
8.7 SPI Registers
The three SPI registers are:
These registers provide control, status, and data storage functions.
8.7.1 Serial Peripheral Control Register
SPIE — Serial Peripheral Interrupt Enable Bit
SPE — Serial Peripheral System Enable Bit
DWOM — Port D Wired-OR Mode Bit
Freescale Semiconductor
Set the SPE bit to 1 to request a hardware interrupt sequence each time the SPIF or MODF status flag
is set. SPI interrupts are inhibited if this bit is clear or if the I bit in the condition code register is 1.
When the SPE bit is set, the port D bit 2, 3, 4, and 5 pins are dedicated to the SPI function. If the SPI
is in the master mode and DDRD bit 5 is set, then the port D bit 5 pin becomes a general-purpose
output instead of the SS input.
DWOM affects all port D pins.
0 = SPI system interrupts disabled
1 = SPI system interrupts enabled
0 = SPI system disabled
1 = SPI system enabled
0 = Normal CMOS outputs
1 = Open-drain outputs
Serial peripheral control register (SPCR)
Serial peripheral status register (SPSR)
Serial peripheral data register (SPDR)
Address:
Reset:
Read:
Write:
U = Unaffected
$1028
SPIE
Figure 8-3. Serial Peripheral Control Register (SPCR)
Bit 7
0
SPE
6
0
M68HC11E Family Data Sheet, Rev. 5.1
DWOM
5
0
MSTR
4
0
CPOL
3
0
CPHA
2
1
SPR1
U
1
SPR0
Bit 0
U
SPI Registers
123

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