MC68HC711E9FU Freescale Semiconductor, MC68HC711E9FU Datasheet - Page 147

• Manufacturer Part Number: MC68HC711E9FU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711E9FU

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 12KB
• Total Internal Ram Size: 512Byte
• # I/os (max): 38
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

PAII and PAIF — Pulse Accumulator Input Edge Interrupt Enable Bit and Flag
Freescale Semiconductor
The PAIF status bit is automatically set each time a selected edge is detected at the PA7/PAI/OC1 pin.
To clear this status bit, write to the TFLG2 register with a 1 in the corresponding data bit position (bit
4). The PAII control bit allows configuring the pulse accumulator input edge detect for polled or
interrupt-driven operation but does not affect setting or clearing the PAIF bit. When PAII is 0, pulse
accumulator input interrupts are inhibited, and the system operates in a polled mode. In this mode, the
PAIF bit must be polled by user software to determine when an edge has occurred. When the PAII
control bit is set, a hardware interrupt request is generated each time PAIF is set. Before leaving the
interrupt service routine, software must clear PAIF by writing to the TFLG2 register.
M68HC11E Family Data Sheet, Rev. 5.1
Pulse Accumulator
147