E28F320J3A110 Intel, E28F320J3A110 Datasheet - Page 34

• Manufacturer Part Number: E28F320J3A110
• Manufacturer: Intel

Specifications of E28F320J3A110

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 22/21Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 4M/2M
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

256-Mbit J3 (x8/x16)
9.1.4
9.1.5
34
Standby
CE0, CE1, and CE2 can disable the device (see
This manipulation of CEx substantially reduces device power consumption. D[15:0] outputs are
placed in a high-impedance state independent of OE#. If deselected during block erase, program, or
lock-bit configuration, the WSM continues functioning, and consuming active power until the
operation completes.
Reset/Power-Down
RP# at V
In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and
turns off numerous internal circuits. RP# must be held low for a minimum of t
required after return from reset mode until initial memory access outputs are valid. After this wake-
up interval, normal operation is restored. The CUI is reset to read array mode and Status Register is
set to 0x80.
During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In
default mode, STS transitions low and remains low for a maximum time of t
reset operation is complete. Memory contents being altered are no longer valid; the data may be
partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time
t
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash memory. Automated flash memories provide
status information when accessed during block erase, program, or lock-bit configuration modes. If
a CPU reset occurs with no flash memory reset, proper initialization may not occur because the
flash memory may be providing status information instead of array data. Intel StrataFlash
memory family devices allow proper initialization following a system reset through the use of the
RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system
CPU.
PHWL
is required after RP# goes to logic-high (V
IL
initiates the reset/power-down mode.
Table 13 on page
IH
) before another command can be written.
33) and place it in standby mode.
PLPH
PLPH
+ t
. Time t
PHRH
Datasheet
®
until the
PHQV
is