E28F320J3A110 Intel, E28F320J3A110 Datasheet - Page 39

• Manufacturer Part Number: E28F320J3A110
• Manufacturer: Intel

Specifications of E28F320J3A110

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 22/21Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 4M/2M
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

10.2
10.2.1
Datasheet
Table 17. Read Identifier Codes
Read Identifier Codes
The Read identifier codes operation outputs the manufacturer code, device-code, and the block
lock configuration codes for each block (See
details on issuing the Read Device Identifier command). Page-mode reads are not supported in this
read mode. To terminate the operation, write another valid command. Like the Read Array
command, the Read Identifier Codes command functions independently of the V
command is valid only when the WSM is off or the device is suspended. Following the Read
Identifier Codes command, the following information can be read.
Read Status Register
The Status Register may be read to determine when a block erase, program, or lock-bit
configuration is complete and whether the operation completed successfully. It may be read only
after the specified time W12 (see
command, all subsequent read operations output data from the Status Register until another valid
command is written. Page-mode reads are not supported in this read mode. The Status Register
contents are latched on the falling edge of OE# or the first edge of CE0, CE1, or CE2 that enables
the device (see
device must be disabled before further reads to update the Status Register latch. The Read Status
Register command functions independently of the V
During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid
until the Write State Machine completes or suspends the operation. Device I/O signals D[6:0] and
D[15:8] are placed in a high-impedance state. When the operation completes or suspends (check
SR.7), all contents of the Status Register are valid when read.
Manufacture Code
Device Code
Block Lock Configuration
• Block Is Unlocked
• Block Is Locked
• Reserved for Future Use
NOTES:
1. A0 is not used in either x8 or x16 modes when obtaining the identifier
2. X selects the specific block’s lock configuration code.
3. D[7:1] are invalid and should be ignored.
codes. The lowest order address line is A1. Data is always presented
on the low byte in x16 mode (upper byte contains 00h).
Table 13, “Chip Enable Truth Table” on page
Code
128-Mbit
256-Mbit
32-Mbit
64-Mbit
Table 9, “Write Operations” on page
Address
X
00000
00001
00001
00001
00001
0002
Section 9.2, “Device Commands” on page 35
(2)
(1)
PEN
voltage.
(00) 1D
(00) 89
(00) 16
(00) 17
(00) 18
D0 = 0
D0 = 1
D[7:1]
Data
33). OE# must toggle to V
26). After writing this
256-Mbit J3 (x8/x16)
PEN
voltage. This
IH
or the
for
39