MPC948FA ON Semiconductor, MPC948FA Datasheet

MPC948FA

Manufacturer Part Number

MPC948FA

Description

Manufacturer

ON Semiconductor

Datasheet

1.MPC948FA.pdf (6 pages)

Specifications of MPC948FA

Lead Free Status / Rohs Status

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Low Voltage 1:12 Clock

Distribution Chip

features the capability to select either a differential LVPECL or a LVTTL

compatible input. The 12 outputs are LVCMOS or LVTTL compatible and

feature the drive strength to drive 50

lines. With output–to–output skews of 350ps, the MPC948 is ideal as a

clock distribution chip for the most demanding of synchronous systems.

For a similar product targeted at a lower price/performance point, please

consult the MPC947 data sheet.

LOW logic states, the output buffers of the MPC948 are ideal for driving

series terminated transmission lines. More specifically, each of the 12

MPC948 outputs can drive two series terminated 50 transmission lines.

With this capability, the MPC948 has an effective fanout of 1:24 in

applications where each line drives a single load. With this level of fanout,

the MPC948 provides enough copies of low skew clocks for high

performance synchronous systems, including use as a clock distribution

chip for the L2 cache of a PowerPC 620 based system.

MC100LVE111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input

provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In

addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH

on the TTL_CLK_Sel pin will select the TTL level clock input.

for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control

is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test,

the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate input will force all of the outputs into

high impedance. Note that all of the MPC948 inputs have internal pullup resistors.

cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.

PowerPC is a trademark of International Business Machines Corporation.

1/97

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Motorola, Inc. 1997

Clock Distribution for PowerPC

LVPECL or LVCMOS/LVTTL Clock Input

350ps Maximum Output–to–Output Skew

Drives Up to 24 Independent Clock Lines

Maximum Output Frequency of 150MHz

Synchronous Output Enable

Tristatable Outputs

32–Lead TQFP Packaging

3.3V V CC Supply Voltage

The MPC948 is a 1:12 low voltage clock distribution chip. The device

With an output impedance of approximately 7 , in both the HIGH and

The differential LVPECL inputs of the MPC948 allow the device to interface directly with a LVPECL fanout buffer like the

All of the control inputs are LVCMOS/LVTTL compatible. The MPC948 provides a synchronous output enable control to allow

The MPC948 is fully 3.3V compatible. The 32–lead TQFP package was chosen to optimize performance, board space and

620 L2 Cache

series terminated transmission

REV 3

DISTRIBUTION CHIP

32–LEAD TQFP PACKAGE

LOW VOLTAGE

MPC948

1:12 CLOCK

CASE 873A–02

FA SUFFIX

Related parts for MPC948FA

MPC948FA Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage 1:12 Clock Distribution Chip The MPC948 is a 1:12 low voltage clock distribution chip. The device features the capability to select either a differential LVPECL or a LVTTL compatible input. The 12 outputs are ...

Page 2

MPC948 PECL_CLK PECL_CLK TTL_CLK TTL_CLK_Sel Sync_OE Tristate VCCO GND 28 MPC948 Q1 29 VCCO GND Figure 2. 32–Lead Pinout (Top View) ...

Page 3

ABSOLUTE MAXIMUM RATINGS* Symbol Parameter V CC Supply Voltage V I Input Voltage I IN Input Current T Stor Storage Temperature Range * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to ...

Page 4

MPC948 Driving Transmission Lines The MPC948 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. ...

Page 5

–T– DETAIL –Z– –AB– SEATING –AC– PLANE 0.10 (0.004 DETAIL AD TIMING SOLUTIONS BR1333 — Rev 6 OUTLINE ...

Page 6

MPC948 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out ...

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