LH28F160BVHE-BTL90 Sharp Electronics, LH28F160BVHE-BTL90 Datasheet - Page 15

• Manufacturer Part Number: LH28F160BVHE-BTL90
• Manufacturer: Sharp Electronics

Specifications of LH28F160BVHE-BTL90

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

4.6 Word/Byte Write Command
Word/byte write is executed by a two-cycle
sequence. Word/byte
alternate 10H) is written, followed by a second write that
specifies the address and data (latched on the rising edge
of WE#). The WSM then takes over, controlling the
word/byte
After the word/byte write sequence is written, the device
automatically outputs status register data when read (see
Figure 6). The CPU can detect the completion of the
word/byte write event by analyzing the RY/BY# pin or
status register bit SR.7.
When word/byte write is complete, status register bit SR.4
should be checked. If word/byte write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for “1”s that do not successfully write
to “0”s. The CUI remains in read status register mode until
it receives another command.
Reliable
Vr-,=2.7V-3.6V
high voltage, memory contents are protected against
word/byte writes. If word/byte
V&V,,,
to “1”. Successful word/byte write for boot blocks requires
that the corresponding if set, that WP#=V,,
If word/byte write is attempted to boot block when the
corresponding WP#=V,
be set to
VIH<Rl%<VHH p reduce spurious results and should not be
attempted.
SHARP
word/byte
write and write verify algorithms internally.
status register bits SR.3 and SR.4 will be set
“1”.
and VPP=VPPHrj2. In the absence of this
Word/byte
writes
write
or RP#=V,,,
setup (standard 40H
can
write is attempted while
write
only
SR. 1 and SR.4 will
operations
or RP#=V,.
occur
command
when
with
LHF16Vll
or
4.7 Block Erase Suspend Command
The Block Erase Suspend command allows block-erase
predetermined point in the algorithm. The device outputs
RY/BY#
read data from blocks other than that which is suspended.
during erase suspend to program data in other blocks.
erase suspended, status register bit SR.7 will return to “0”
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is written
to the flash memory, the WSM will continue the block
erase process. Status register bits SR.6 and SR.7 will
automatically clear and RY/BY# will return to VOL. After
the Erase Resume command is written,
automatically outputs status register data when read (see
Figure 7). V,,
level used for block erase) while block erase is suspended.
RP# must also remain at V,, or V,
used for block erase). WP# must also remain at V, or V,,
(the same WP# level used for block erase). Block erase
cannot resume until word/byte write operations initiated
during block erase suspend have completed.
interruption to read or word/byte write data in another
block of memory. Once the block-erase process starts,
writing the Block Erase Suspend command requests that
the WSM
status register data when read after the Block Erase
Suspend command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to “1”).
twHRz2 defines the block erase suspend latency.
At this point, a Read Array command can be written to
A Word/Byte Write command sequence can also be issued
Using the Word/Byte
Section 4.8), a word/byte
suspended. During a word/byte write operation with block
and the RY/BY# output will transition to VOL. However,
SR.6 will remain “1” to indicate block erase suspend
status.
will
suspend the block
also transition to High Z. Specification
must remain at V,,,,,z
Write
write operation can also be
Suspend command (see
erase sequence at a
(the same RP# level
(the same V,,
the device
Rev. 1.02
13
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