LH28F160BVHE-BTL90 Sharp Electronics, LH28F160BVHE-BTL90 Datasheet - Page 23

• Manufacturer Part Number: LH28F160BVHE-BTL90
• Manufacturer: Sharp Electronics

Specifications of LH28F160BVHE-BTL90

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

deep power-down
After block erase or word/byte
transitions down to V,,,,,
array mode via the Read Array command if subsequent
access to the memory array is desired.
5.6 Power-Up/Down Protection
The device is designed to offer protection
accidental block erasure or word/byte
power
indifferent
powers-up first. Internal circuitry resets the CUI to read
array mode at power-up.
RP# transitions to V,
write, RY/BY# will remain low until the reset operation is
complete. Then, the operation will abort and the device
will enter deep power-down.
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
restored. Device power-off or RP# transitions to V, clear
the status register.
The CUI latches commands issued by system software and
is not altered by V,
Its state is read array mode upon power-up, after exit from
5.5 VCC, Vpp, RP# Transitions
Block erase and word/byte write are not guaranteed if V,,
falls outside of a valid V,,,,,,
a valid 2.lV-3.6V range, or RP##V,, or V,,.
is detected, status register bit SR.3 is set to “1” along with
SR.4 or SR.5, depending on the attempted operation. If
SI-IARP
transitions.
as to which power supply (V,,
or after V,, transitions below VLKo.
Upon
or CE# transitions or WSM actions.
during block erase or word/byte
the CUI must be placed in read
power-up,
The aborted operation may
range, V,- falls outside of
write, even after V,,
the device
writing
If V,, error
or V,,)
against
during
LHF16Vll
is
battery
battery life because data is retained when system power is
removed.
In addition, deep power-down
low power consumption even when system power is
applied. For example, portable computing products and
other power sensitive applications that use an array of
devices for solid-state storage can consume negligible
power by lowering RP# to V, standby or sleep modes. If
access is again needed, the devices can be read following
*e
first raised to VI,. See AC Characteristics-
and Write Operations and Figures 11, 12, 13 and 14 for
more information.
either to VI,
command sequence architecture provides added level of
protection against data alteration.
WP# provide additional protection from inadvertent code
or data alteration. The device is disabled while RP#=V,
regardless of its control inputs state.
5.7 Power Dissipation
When designing portable systems, designers must consider
operation, but also for data retention during system idle
time. Flash
A system designer must guard against spurious writes for
V,- voltages above V,,,
WE# and CE# must be low for a command write, driving
tPHQV
power
md
memory’s
tPHWL
will inhibit writes. The GUI’s two-step
consumption
wake-up cycles required after RP# is
nonvolatility
when V,, is active. Since both
not only during device
mode ensures extremely
increases usable
Read Only
Rev. 1.02
21