MT46V8M16TG-75Z Micron Technology Inc, MT46V8M16TG-75Z Datasheet
MT46V8M16TG-75Z
Specifications of MT46V8M16TG-75Z
Related parts for MT46V8M16TG-75Z
MT46V8M16TG-75Z Summary of contents
Page 1
... RCD) • Revision Notes: 1. Not recommended for new designs Clock Rate (MHz 2 167 200 167 n/a 133 n/a 133 n/a 1 128Mb: x4, x8, x16 DDR SDRAM (TSOP only) 1 Data Out Access Window Window 1.6ns ±0.70ns 2.0ns ±0.70ns 2.5ns ±0.75ns 2.5ns ±0.75ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 2
... Example Part Number: MT46V8M16P-6T:D Configuration Package 32M4 16M8 8M16 Package 400-mil TSOP TG 400-mil TSOP (Pb-free 128Mb: x4, x8, x16 DDR SDRAM 16 Meg Meg Meg banks 4K 4K (A0–A11) 4K (A0–A11) 4 (BA0, BA1) 4 (BA0, BA1) 1K (A0–A9) 512 (A0–A8) Yes Yes Yes ...
Page 3
... SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 POWER-DOWN (CKE Not Active .80 PDF: 09005aef816fd013/Source: 09005aef82a95a3a 128Mb_DDRTOC.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 128Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 ©2004 Micron Technology, Inc. All rights reserved. Table of Contents ...
Page 4
... CKEH = Exit power down CKEL = Enter power down EMR = Extended mode register LMR = LOAD MODE REGISTER MR = Mode register Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 128Mb: x4, x8, x16 DDR SDRAM State Diagram Self refresh REFS REFSX Idle ...
Page 5
... READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths locations. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access ...
Page 6
... Functional Block Diagrams The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits internally configured as a 4-bank DRAM. Figure 3: 32 Meg x 4 Functional Block Diagram CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTERS 14 12 A0–A11, ADDRESS ...
Page 7
... DECODER SENSE AMPLIFIERS I/O GATING 2 DM MASK LOGIC BANK CONTROL LOGIC 2 COLUMN- 8 ADDRESS 9 COUNTER/ LATCH 1 7 128Mb: x4, x8, x16 DDR SDRAM Functional Block Diagrams BANK3 BANK2 DATA READ MUX LATCH 8 DQS GENERATOR COL0 INPUT 16 REGISTERS 1 1 MASK ...
Page 8
... WE# 21 CAS# CAS# 22 RAS# RAS# 23 CS# CS BA0 BA0 26 BA1 BA1 27 A10/AP A10/ Micron Technology, Inc., reserves the right to change products or specifications without notice. 8 128Mb: x4, x8, x16 DDR SDRAM Pin Assignments and Descriptions x8 x4 x16 DQ7 NF 65 DQ15 DQ14 DQ13 DQ6 DQ3 ...
Page 9
... and x8. Supply Power supply. Supply DQ power supply: Isolated on the die for improved noise immunity. 9 128Mb: x4, x8, x16 DDR SDRAM Pin Assignments and Descriptions LOW level after V is applied and until DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 10
... Do not use: Must float to minimize noise on Type Description Input Address inputs A12 and A13 for 256Mb, 512Mb, and 1Gb devices. 10 128Mb: x4, x8, x16 DDR SDRAM Pin Assignments and Descriptions . V REF Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 11
... MAX Micron Technology, Inc., reserves the right to change products or specifications without notice. 11 128Mb: x4, x8, x16 DDR SDRAM Package Dimensions GAGE PLANE +0.10 –0.05 DETAIL A ©2004 Micron Technology, Inc. All rights reserved. 0.25 0.80 TYP ...
Page 12
... REF Power- Continuous burst = 0mA t t RFC = RFC (MIN) t RFC = 15.6µs Standard Low power ( (MIN); Address and control 12 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – +2.5V ±0.2V (-6T, -75E, -75Z, -75); DD -6T -75E -75Z/-75 Units Notes I 0 115 125 110 105 ...
Page 13
... Continuous burst I = 0mA RFC = RFC (MIN) t RFC = 15.6µs I Standard Low power ( (MIN); Address and control 13 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – +2.5V ±0.2V (-6T, -75E, -75Z, -75); DD -6T -75E -75Z/-75 Units I 0 125 125 115 110 135 135 135 125 ...
Page 14
... Micron Technology, Inc., reserves the right to change products or specifications without notice. 14 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – RFC REFI 9 n/a n/a 8 n/a n/a 10 n/a n/a 11 n/a n/a 9 n/a n/a 9 n/a n/a 8 n/a ...
Page 15
... OUT Q - 0.373V, minimum , minimum OLR OUT , REF ) 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Absolute Maximum Value –1V to +3.6V –1V to +3.6V –1V to +3.6V –0. +0.5V DD –55°C to +150°C 50mA Min Max Units +2.5 +2.7 +2.5 +2.7 0.49 × 0.51 × ...
Page 16
... OUT , REF ) +2.5V ±0.2V +2.5V ±0. +2.6V ±0.1V for -5B) DD Symbol 0.49 × V REF AC 16 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and +2.5V ±0.2V Min Max +2.3 +2.7 +2.3 +2 0.04 REF REF 0.3 REF DD –0 0.15 REF – ...
Page 17
... V TT 25Ω Reference 25Ω point Micron Technology, Inc., reserves the right to change products or specifications without notice. 17 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Receiver ©2004 Micron Technology, Inc. All rights reserved ...
Page 18
... DD Symbol 0.5 × MIN when static and is centered around 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Min Max 1.15 1.35 –0 0 0 0.2 0.5 × 0 Maximum clock level Minimum clock level 0.3V or more negative than V DD Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
Page 19
... Delta input capacitance: CK, CK# Input/output capacitance: DQ, LDQS, UDQS, LDM, UDM Input capacitance: Command and address Input capacitance: CK, CK# Input capacitance: CKE PDF: 09005aef816fd013/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Symbol Min DC – – ...
Page 20
... REFC t RFC 128Mb, 256Mb, 512Mb t RFC 1Gb t 128Mb REFI t 256Mb, 512Mb, 1Gb REFI RPRE t RPST t RRD t VTD t WPRE 20 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -5B Min Max Units –0.70 +0. 0. 0.45 0.55 CK 0.40 – ...
Page 21
... DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev +2.6V ±0.1V +2.6V ±0.1V DD Symbol t WPRES t WPST WTR t 128Mb, 256Mb, 512Mb XSNR t 1Gb XSNR t XSRD n/a 21 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -5B Min Max Units 0 – 0.4 0 – – – ns 126 – ...
Page 22
... REFC – t REFC – t REFI – t REFI – t RFC 72 t RFC – RPRE 0.9 22 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC 1 -6T (TSOP) -75E Max Min Max Min Max 0.55 0.45 0.55 0. 7.5 13 7.5 13 0.55 0.45 ...
Page 23
... Exit SELF REFRESH-to-READ command Data valid output window (DVW) Notes (FBGA) available in 256Mb and 512Mb densities only. PDF: 09005aef816fd013/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and (FBGA) -6T (TSOP) Symbol Min ...
Page 24
... REFC 256Mb, 512Mb, 1Gb t 128Mb REFI t 256Mb, REFI 512Mb, 1Gb t 128Mb, RFC 256Mb, 512Mb t RFC 1Gb 24 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -75Z -75 Min Max Min Max –0.75 +0.75 –0.75 +0.75 0.45 0.55 0.45 0.55 7.5 13 7.5 13 7.5 ...
Page 25
... Note: 32 apply to entire table; 0°C ≤ T Speed Slew Rate -75/-75Z/-75E 0.500 V/ns -75/-75Z/-75E 0.400 V/ns -75/-75Z/-75E 0.300 V/ns PDF: 09005aef816fd013/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -75Z Symbol Min Max – t RPRE 0 ...
Page 26
... Specified values are obtained specifications are tested after the device is properly initialized and is averaged at = +2.5V ±0.2V 25° OUT 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -to-V swing 1.5V in the test environ- IH (or to the crossing point for CK/CK#), REF ( ) and ...
Page 27
... DDR). However, an AUTO REFRESH command must be asserted at least once every 70.3µs (140.6µs for 128Mb DDR); burst refreshing or posting by the DRAM controller greater than 8 REFRESH cycles is not allowed. 25. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device ...
Page 28
... V-I curve of Figure 11 on page 29. and voltage will lie within the outer bounding lines of the V-I curve of Figure 12 on page 29. 28 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC - 7.5ns -75E / - 7.5ns - 6ns ...
Page 29
... V-I curve of Figure 13 on page 30. and voltage will lie within the outer bounding lines of the V-I curve of Figure 14. 29 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC 2.0 2.5 2 ...
Page 30
... V Q must track each other DQSCK (MAX DQSCK (MIN) + RPRE (MAX) condition. 30 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC 2.0 2.5 2.0 2.5 level and the referenced test DD pulse width ≤ 3ns, and the pulse t RPST (MAX) condition. ...
Page 31
... Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset followed by 200 clock cycles before any READ command. 53. This is the DC voltage supplied at the DRAM and is inclusive of all noise MHz. Any noise above 20 MHz at the DRAM generated from any source other than that of the DRAM itself may not exceed the DC voltage range of 2.6V ± ...
Page 32
... PDF: 09005aef816fd013/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Nominal Min Max Low 4.6 9.6 –6.1 9.2 18.2 –12.2 13.8 26.0 – ...
Page 33
... PDF: 09005aef816fd013/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Nominal Min Max Low 2.6 5.0 –3.5 5.2 9.9 –6.9 7.8 14.6 – ...
Page 34
... Table 26: Truth Table 2 – DM Operation Used to mask write data, provided coincident with the corresponding data Name (Function) Write enable Write inhibit PDF: 09005aef816fd013/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 128Mb: x4, x8, x16 DDR SDRAM CS# RAS# CAS# WE ...
Page 35
... RCD is met, the bank will be in the “row active” state. auto precharge enabled and ends when will be in the idle state. auto precharge enabled and ends when will be in the idle state. 35 128Mb: x4, x8, x16 DDR SDRAM is HIGH (see Table 30 on page 38) and has been met. t RCD has been met ...
Page 36
... This table applies when CKE after PDF: 09005aef816fd013/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev met. Once RFC is met, the DDR SDRAM will be in the all banks idle state. t and ends when MRD has been met. Once all banks idle state met ...
Page 37
... The minimum delay from a READ or WRITE command with auto precharge enabled command to a different bank is summarized in Table 29. To Command PRECHARGE ACTIVE PRECHARGE ACTIVE 37 128Mb: x4, x8, x16 DDR SDRAM t RP has been met. t RCD has been met. No data t WR ends, with t RP) begins. This device supports ...
Page 38
... H Notes: 1. CKE clock edge. 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. COMMAND MAND 4. All states and sequences not shown are illegal or reserved. 5. CKE must not drop LOW during a column access. For a READ, this means CKE must stay ...
Page 39
... PDF: 09005aef816fd013/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN CK# CK CKE HIGH CS# Row Bank DON’T CARE 39 128Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. Commands ...
Page 40
... Ai is the most significant column address bit for a given density ( HIGH Col EN AP DIS AP Bank DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. 40 128Mb: x4, x8, x16 DDR SDRAM Commands ©2004 Micron Technology, Inc. All rights reserved. ...
Page 41
... All banks must be idle before an AUTO REFRESH command is issued. SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). ...
Page 42
... DLL bit (set LMR command is issued, the same operating parameters should be utilized as in step 11. 20. Wait at least 21. At this point the DRAM is ready for any valid command. At least 200 clock cycles with CKE HIGH are required between step 11 (DLL RESET) and any READ command. PDF: 09005aef816fd013/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F ...
Page 43
... Issue AUTO REFRESH command Assert NOP or DESELECT for t RFC time Optional LMR command to clear DLL bit Assert NOP or DESELECT for t MRD time DRAM is ready for any valid command Micron Technology, Inc., reserves the right to change products or specifications without notice. 43 128Mb: x4, x8, x16 DDR SDRAM Operations © ...
Page 44
... V , and V + 0.3V. Alternatively, V REF are 0V, provided a minimum of 42 ohms of series resistance is used DD DD supply and the input pin. Once initialized 128Mb: x4, x8, x16 DDR SDRAM Tc0 Td0 Te0 ( ( ( ( ( ( ) ) ) ) ...
Page 45
... REGISTER DEFINITION Mode Register The mode register is used to define the specific DDR SDRAM mode of operation. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure 21. The mode register is programmed via the LMR command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or until the device loses power (except for bit A8, which is self- clearing) ...
Page 46
... Burst Length (BL) Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable for both READ and WRITE bursts, as shown in Figure 21 on page 45. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command locations are available for both the sequential and the interleaved burst types ...
Page 47
... READ NOP DQS CK# CK READ NOP CL = 2.5 DQS CK# CK READ NOP DQS DQ TRANSITIONING DATA 47 128Mb: x4, x8, x16 DDR SDRAM T2 T2n T3 T3n NOP NOP T2 T2n T3 T3n NOP NOP T2 T3 T3n NOP NOP DON’T CARE AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 48
... CL = 2.5 75 ≤ f ≤ 167 75 ≤ f ≤ 167 75 ≤ f ≤ 133 75 ≤ f ≤ 133 75 ≤ f ≤ 133 Micron Technology, Inc., reserves the right to change products or specifications without notice. 48 128Mb: x4, x8, x16 DDR SDRAM Operations 133 ≤ f ≤ 200 – – – – ...
Page 49
... RCD specification. t RCD specification of 20ns with a 133 MHz clock (7.5ns period ≤ 3 (Figure 24 also shows the same case for RCD (MIN)/ 49 128Mb: x4, x8, x16 DDR SDRAM Address Bus Extended Mode DS DLL Register (Ex) E0 DLL 0 Enable ...
Page 50
... CK and CK#). Figure 25 on page 52 shows the general timing for each possible CL setting. DQS is driven by the DDR SDRAM along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with the last data-out element is known as the read postamble ...
Page 51
... RP have been met. Part of the row precharge time is hidden during the access of the last data elements. PDF: 09005aef816fd013/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 128Mb: x4, x8, x16 DDR SDRAM t DQSS (NOM) case is shown; the t DQSS [MIN] and Micron Technology, Inc ...
Page 52
... READ NOP NOP Bank a, Col 2 READ NOP NOP Bank a, Col AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 52 128Mb: x4, x8, x16 DDR SDRAM T2n T3 T3n T4 NOP NOP n T2n T3 T3n T4 NOP NOP T3n T4 T4n NOP NOP DO n DON’ ...
Page 53
... Bank, Col n Col 2 READ NOP READ Bank, Bank, Col n Col AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 53 128Mb: x4, x8, x16 DDR SDRAM Operations T2n T3 T3n T4 T4n NOP NOP DO b T2n T3 T3n T4 T4n NOP NOP ...
Page 54
... NOP NOP READ Bank, Col AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 54 128Mb: x4, x8, x16 DDR SDRAM Operations T3n T4 T5 T5n NOP NOP DO b T3n T4 T5 T5n NOP NOP DO b T4n T3n T4 T5 ...
Page 55
... Col n Col x Col 2 READ READ READ Bank, Bank, Bank, Col n Col x Col AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 55 128Mb: x4, x8, x16 DDR SDRAM Operations T3 T3n T4 T4n T5 READ NOP Bank, Col T2n T3 T3n T4 T4n ...
Page 56
... NOP Bank a, Col 2 BST 1 READ NOP Bank a, Col AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 56 128Mb: x4, x8, x16 DDR SDRAM Operations T2n T3 T4 NOP NOP T2n T3 T4 NOP NOP T3n T4 NOP NOP DO n DON’T CARE TRANSITIONING DATA © ...
Page 57
... BST Bank, Col 2 READ BST NOP Bank a, Col AC, DQSCK, and Micron Technology, Inc., reserves the right to change products or specifications without notice. 57 128Mb: x4, x8, x16 DDR SDRAM T2n T3 T4 T4n WRITE NOP Bank, Col b t DQSS (NOM T2n T3 T3n T4 NOP WRITE Bank, ...
Page 58
... RAS (MIN) is met, a READ command with auto precharge enabled would cause AC, DQSCK, and DQSQ. t RAS (MIN) is met. Micron Technology, Inc., reserves the right to change products or specifications without notice. 58 128Mb: x4, x8, x16 DDR SDRAM Operations T2n T3 T3n T4 NOP NOP t RP T2n T3 T3n ...
Page 59
... DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev NOP READ NOP t IH Col Bank RCD t RAS (MIN) 59 128Mb: x4, x8, x16 DDR SDRAM T5 T5n T6 T6n PRE NOP NOP ALL BANKS ONE BANK 5 Bank DQSCK (MIN) t RPST RPRE (MIN (MIN) t DQSCK (MAX RPST RPRE DO ...
Page 60
... DQ (last data valid (last data valid) Earliest signal transition Latest signal transition clock transition collectively when a bank is active HP QHS. Micron Technology, Inc., reserves the right to change products or specifications without notice. 60 128Mb: x4, x8, x16 DDR SDRAM T2 T2n T3 T3n DQSQ 2 t DQSQ T2n T3 T2 T2n ...
Page 61
... DQSQ 2 UDQS Data valid window clock transition collectively when a bank is active HP QHS. Micron Technology, Inc., reserves the right to change products or specifications without notice. 61 128Mb: x4, x8, x16 DDR SDRAM Operations T2n T3 T3n DQSQ 2 t DQSQ 2 t DQSQ T2n T3 T3n T2n T3 T3n T2n ...
Page 62
... AC (MAX) are the latest valid signal transitions DQSS [MIN] and DQSS [MAX]) might not be intuitive; they have Micron Technology, Inc., reserves the right to change products or specifications without notice. 62 128Mb: x4, x8, x16 DDR SDRAM Operations T3 T3n T4 T4n T5 t DQSCK 2 (MAX) t DQSCK 2 (MIN) ...
Page 63
... DM, as shown in Figures 44 and 45. After the PRECHARGE command, a subsequent command to the same bank cannot be issued until PDF: 09005aef816fd013/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 128Mb: x4, x8, x16 DDR SDRAM t WTR should be met, as shown in Figure period are written to the internal array; any subsequent data-in Micron Technology, Inc ...
Page 64
... Bank a, Col b t DQSS DQS DQSS DQS DQSS DQS DON’T CARE 64 128Mb: x4, x8, x16 DDR SDRAM T2 T2n T3 NOP NOP TRANSITIONING DATA Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. Operations ...
Page 65
... WRITE NOP WRITE Bank, Bank, Col b Col n t DQSS DI b Micron Technology, Inc., reserves the right to change products or specifications without notice. 65 128Mb: x4, x8, x16 DDR SDRAM Operations T2n T3 T3n T4 T4n NOP NOP DI n DON’T CARE TRANSITIONING DATA ©2004 Micron Technology, Inc. All rights reserved. ...
Page 66
... WRITE NOP Bank, Col b t DQSS T1n CK WRITE WRITE Bank, Bank, Col b Col x t DQSS (NOM 128Mb: x4, x8, x16 DDR SDRAM T2 T2n T3 T4 T4n NOP WRITE NOP Bank, Col DON’T CARE TRANSITIONING DATA T2 T2n T3 T3n T4 T4n WRITE WRITE WRITE Bank, ...
Page 67
... T1 T1n T2 T2n T3 NOP NOP NOP t WTR Micron Technology, Inc., reserves the right to change products or specifications without notice. 67 128Mb: x4, x8, x16 DDR SDRAM Operations READ NOP NOP Bank a, Col DON’T CARE TRANSITIONING DATA t WTR is not required, and the READ ©2004 Micron Technology, Inc. All rights reserved. ...
Page 68
... T1n T2 T2n T3 NOP NOP READ t WTR Bank a, Col Micron Technology, Inc., reserves the right to change products or specifications without notice. 68 128Mb: x4, x8, x16 DDR SDRAM Operations T3n T4 T5 T5n NOP NOP DON’T CARE TRANSITIONING DATA ©2004 Micron Technology, Inc. All rights reserved. ...
Page 69
... T1 T1n T2 T2n T3 NOP NOP READ t WTR Bank a, Col 128Mb: x4, x8, x16 DDR SDRAM T3n T4 T5 T5n NOP NOP DON’T CARE TRANSITIONING DATA Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. ...
Page 70
... DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev T1n T2 T2n T3 NOP NOP NOP Micron Technology, Inc., reserves the right to change products or specifications without notice. 70 128Mb: x4, x8, x16 DDR SDRAM Operations PRE NOP NOP Bank all) DON’T CARE TRANSITIONING DATA not required, and ...
Page 71
... T2 T2n T3 NOP NOP NOP Micron Technology, Inc., reserves the right to change products or specifications without notice. 71 128Mb: x4, x8, x16 DDR SDRAM Operations T3n T4 T4n T5 NOP PRE t RP Bank all) DON’T CARE TRANSITIONING DATA ©2004 Micron Technology, Inc. All rights reserved. T6 NOP ...
Page 72
... T1n T2 T2n T3 NOP NOP NOP 128Mb: x4, x8, x16 DDR SDRAM T3n T4 T4n T5 PRE NOP Bank all) DON’T CARE TRANSITIONING DATA Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. Operations T6 NOP ...
Page 73
... Bank x t RCD t RAS t DQSS (NOM WPRES WPRE Micron Technology, Inc., reserves the right to change products or specifications without notice. 73 128Mb: x4, x8, x16 DDR SDRAM T5 T5n T6 T7 NOP 1 NOP 1 NOP DQSL DQSH WPST DON’T CARE TRANSITIONING DATA ©2004 Micron Technology, Inc. All rights reserved. ...
Page 74
... Bank x t RCD t RAS t DQSS (NOM WPRES WPRE Micron Technology, Inc., reserves the right to change products or specifications without notice. 74 128Mb: x4, x8, x16 DDR SDRAM T5 T5n NOP NOP NOP DQSL DQSH WPST DON’T CARE TRANSITIONING DATA ©2004 Micron Technology, Inc. All rights reserved. ...
Page 75
... DQSS (MIN). t DQSS (MAX). t RP) is completed. Micron Technology, Inc., reserves the right to change products or specifications without notice. 75 128Mb: x4, x8, x16 DDR SDRAM Operations T2n T3 t DSS 3 TRANSITIONING DATA DON’T CARE t RP) after the t RAS (MIN), as described for ©2004 Micron Technology, Inc. All rights reserved. ...
Page 76
... DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev 2,3 NOP READ NOP Col Bank x t RCD, t RAP RAS (MIN) t RAS has been satisfied. 76 128Mb: x4, x8, x16 DDR SDRAM T5 T5n T6 T6n NOP NOP NOP DQSCK (MIN) t RPST RPRE (MIN (MIN) t DQSCK (MAX RPST RPRE ...
Page 77
... AUTO REFRESH command and the next AUTO REFRESH command fications exceed the JEDEC requirement by one clock. This maximum absolute interval is to allow future support for DLL updates, internal to the DDR SDRAM restricted to AUTO REFRESH cycles, without allowing excessive drift in PDF: 09005aef816fd013/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F ...
Page 78
... DM, DQ, and DQS signals are all “Don’t Care”/High-Z for the operations shown. SELF REFRESH When in the self refresh mode, the DDR SDRAM retains data without external clocking. The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (A DLL reset and 200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are “ ...
Page 79
... XSRD (200 cycles of a valid clock with CKE = HIGH) is required before any READ command can be applied general rule, any time self refresh mode is exited, the DRAM may not re-enter the self refresh mode until all rows have been refreshed via the AUTO REFRESH command at the ...
Page 80
... POWER-DOWN (CKE Not Active) Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in progress, from the issuing of a READ or WRITE command, until completion of the access. Thus a clock suspend is not supported. For READs, an access completion is defined when the read postamble is satisfied; for WRITEs, when the write recovery time ...
Page 81
... REFC Enter 3 power-down mode must always be powered within the specified range. REF ® their respective owners. Micron Technology, Inc., reserves the right to change products or specifications without notice. 81 128Mb: x4, x8, x16 DDR SDRAM Ta0 Ta1 Ta2 t IS NOP VALID VALID Exit power-down mode DON’ ...