IMIC9530CT Cypress Semiconductor Corp, IMIC9530CT Datasheet

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IMIC9530CT

Manufacturer Part Number
IMIC9530CT
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of IMIC9530CT

Function
Clock Generator
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Package Type
TSSOP
Pin Count
48
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant

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Quantity
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Part Number:
IMIC9530CT
Quantity:
20 023
Cypress Semiconductor Corporation
Document #: 38-07033 Rev. *C
Features
Note:
1. A and B banks have separate frequency select and output enable controls. XIN is the frequency of the clock on the device’s XIN pin. OEA and OEB will three-state
• Dedicated clock buffer power pins for reduced noise,
• Input clock frequency of 25 MHz to 33.3 MHz
• Output frequencies of XINx1, XINx2, XINx3 and XINx4
• Output grouped in two banks of five clocks each
• One REF XIN clock output
• SMBus clock control interface for individual clock
• Output clock duty cycle is 50% (± 5%)
• < 250 ps skew between output clocks within a bank
• Output jitter < 250 psec (175 psec with all outputs at the
• Spread Spectrum feature for reduced electromagnetic
• OE pins for entire output bank enable control and
• 48-pin SSOP and TSSOP packages
crosstalk and jitter
disabling and SSCG control and individual back
frequency selection
same frequency)
interference (EMI)
testability
REF.
Block Diagram
SDATA
SB(0,1)
SA(0,1)
SSCG#
IA(0:2)
XOUT
SCLK
XIN
SSCG
Logic
I
Control
Logic
2
C
/N
/N
1
0
0
1
OEA
OEB
PCIX I/O System Clock Generator with EMI
BGOOD#
AGOOD#
CLKB3
CLKA0
CLKA1
CLKA2
CLKA3
CLKA4
CLKB0
CLKB1
CLKB2
CLKB4
REF
198 Champion Court
Table 1. Test Mode Logic Table
HIGH
HIGH
HIGH
HIGH
LOW
OEA
OEB
Pin Configuration
AGOOD#
San Jose
Input Pins
CLKA0
CLKA1
CLKA2
CLKA3
CLKA4
XOUT
VDDA
VDDA
AVDD
HIGH
HIGH
LOW
LOW
VDD
OEA
REF
VSS
VSS
VSS
VSS
VSS
SA1
SB1
SA0
SA1
XIN
IA0
IA1
IA2
X
,
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CA 95134-1709
HIGH
HIGH
LOW
LOW
SA0
SB0
X
Control Features
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Revised October 31, 2005
[1]
Three-state Three-state
2 * XIN
3 * XIN
4 * XIN
SDATA
SCLK
VDD
VSS
VDD
SB1
VSS
CLKB0
CLKB1
CLKB2
VDDB
CLKB3
CLKB4
VSS
BGOOD#
AVDD
AVDD
VSS
OEB
CLKA
CLKB
SB0
VDDB
VSS
SSCG#
VSS
XIN
Output Pins
408-943-2600
C9530
REF
XIN
XIN
XIN
XIN
[+] Feedback

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IMIC9530CT Summary of contents

Page 1

... Note and B banks have separate frequency select and output enable controls. XIN is the frequency of the clock on the device’s XIN pin. OEA and OEB will three-state REF. Cypress Semiconductor Corporation Document #: 38-07033 Rev. *C PCIX I/O System Clock Generator with EMI Table 1. Test Mode Logic Table ...

Page 2

Pin Description [2] [4] Pin Name PWR I/O 3 XIN VDDA I 4 XOUT VDDA O 1 REF VDD O 24* OEA VDD I 25* OEB VDD I 18 AGOOD# VDD O 31 BGOOD# VDD O 6*, 7* SA(0,1) ...

Page 3

Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The ...

Page 4

Byte 0: Function Select Register (continued) Bit @Pup Name 1 0 SA0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set HWSEL Hardware/SMBus frequency control Hardware (pins ...

Page 5

Table 6. Suggested Oscillator Crystal Parameters Parameter Description F Frequency o T Tolerance Operating Mode C Load Capacitance XTAL R Effective Series Resistance (ESR) ESR Internal Crystal Oscillator This device will operate in two input ...

Page 6

C C XINPCB XINDISC C C XOUTPCB XOUTDISC As an example and using this formula for this data sheet’s device, a design that has no discrete loading capacitors (C ) and each of the crystal device PCB traces has a ...

Page 7

Absolute Maximum Conditions Parameter Description V V Core Supply Voltage DD, DDP V Analog Supply Voltage DDA V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J ESD ESD Protection (Human Body Model) ...

Page 8

AC Electrical Specifications (continued) Parameter Description XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ L Long-term Accuracy ACC CLK T CLK Duty Cycle DC T 33MHz CLK Period PERIOD33 T 66MHz ...

Page 9

... Ordering Information Part Number IMIC9530CY IMIC9530CYT IMIC9530CT IMIC9530CTT Lead-free CYI9530ZXC CYI9530ZXCT Document #: 38-07033 Rev. *C Package Type 48-Pin SSOP 48-Pin SSOP – Tape and Reel 48-Pin TSSOP 48-Pin TSSOP – Tape and Reel 48-Pin TSSOP 48-Pin TSSOP – Tape and Reel C9530 Product Flow Commercial, 0° ...

Page 10

... Document #: 38-07033 Rev. *C © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 11

Document History Page Document Title: C9530 PCIX I/O System Clock Generator with EMI Control Features Document #: 38-07033 Issue REV. ECN NO. Date ** 106961 06/12/02 *A 122726 12/17/02 *B 126595 05/14/03 *C 404563 See ECN Document #: 38-07033 Rev. ...

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