CY28159PVC Cypress Semiconductor Corp, CY28159PVC Datasheet

CY28159PVC

Manufacturer Part Number
CY28159PVC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY28159PVC

Function
Clock Generator
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Package Type
SSOP
Pin Count
48
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY28159PVC
Manufacturer:
CY
Quantity:
4 062
Part Number:
CY28159PVC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
1CY28159
Features
Table 1. Frequency Selection
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-07118 Rev. *A
• Eight differential CPU clock outputs
• One PCI output
• One 14.31818-MHz reference clock
• Two 48-MHz clocks
SEL 100/133
Clock Generator for Serverworks Grand Champion Chipset Applications
Block Diagram
SEL100/133
MultSel(0:1)
0
0
0
0
1
1
1
1
SSCG#
XOUT
I_Ref
PD#
XIN
OSC
S0
0
0
1
1
0
0
1
1
VCO
S(0,1)
S1
0
1
0
1
0
1
0
1
Control
I
CPU(0:7), CPU#(0:7)
VDDI
VSSI
133.3MHz
133.3MHz
VDDL
VSSL
100 MHz
100 MHz
100 MHz
200MHz
Hi-Z
N/A
REF
CPU (0:7)
CPU (0:7)#
48M(0,1)/S(0,1)
3V33
3901 North First Street
33.3MHz
33.3MHz
33.3MHz
33.3MHz
33.3MHz
Disable
3V33
• All outputs compliant with Intel
• External resistor for current reference
• Selection logic for differential swing control, test mode,
• 48-pin SSOP and TSSOP packages
Hi-Z
N/A
Hi-Z, power-down and spread spectrum
Pin Configuration
48M0/S0
48M1/S1
SSCG#
CPU0#
CPU1#
CPU2#
CPU3#
XOUT
CPU0
CPU1
CPU2
CPU3
3V33
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
REF
XIN
San Jose
48M(0,1)
48 MHz
Disable
Disable
48 MHz
Disable
48 MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Hi-Z
N/A
CA 95134
Test Mode(recommended)
Revised December 27, 2002
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Test Mode (optional)
®
Normal Operation
Hi-Z all outputs
specifications
Reserved
o7ptional
Optional
Optional
Notes
SEL100/133
VSS
VDDA
VSSA
PD#
VDD
CPU4
CPU4#
VSS
CPU5
CPU5#
VDD
CPU6
CPU6#
VSS
CPU7
CPU7#
VDD
MULT0
MULT1
VSS
VSSA
IREF
VDDA
CY28159
408-943-2600
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CY28159PVC Summary of contents

Page 1

... VCO SEL100/133 PD# S(0,1) Intel is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation Document #: 38-07118 Rev. *A • All outputs compliant with Intel • External resistor for current reference • Selection logic for differential swing control, test mode, Hi-Z, power-down and spread spectrum • ...

Page 2

Pin Description Pin Name I/O 20 SSCG 7,10, 13, 16, CPU(0:7) 42, 39, 36 11, 14, 17, CPU(0:7)# 41, 38, 35 IRef 1 3V33 44 PD 48M(0,1), S(0,1) 48 SEL100/133 23 XOUT 22 XIN ...

Page 3

Table 2. Group Offset Specifications Group Offset CPU to 3V33 No requirement CPU to REF No requirement Test Load Configuration The following shows test load configurations for the different Host Clock Outputs.(MULTsel1 = 0, MULTsel0 =1 CPUT VDD MULTSEL CPUT# ...

Page 4

Document #: 38-07118 Rev ...

Page 5

Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic Interfer- Table 4. Spectrum Spreading Selection Table Unspread Frequency in MHz 100 133.3 200 Power Management Functions Table 5. Host Swing ...

Page 6

Buffer Characteristics Current Mode CPU Clock Buffer Characteristics The current mode output buffer detail and current reference circuit details are contained elsewhere in this datasheet. The following parameters are used to specify output buffer charac- teristics: VDD3 (3.3V +/- 5%) ...

Page 7

Table 7. Current Accuracy Conditions Iout V = nominal (3.30V) All combinations of M0, M1 and Rr shown in DD Host Swing Select Function, Table 5 on page 5 Iout V = 3.30 ± 5% All combinations of M0, m1 ...

Page 8

Maximum Ratings Input Voltage Relative to V :...............................V SS Input Voltage Relative ............. V DDQ DD Storage Temperature: ................................ – 150 C Operating Temperature: .................................... +70 C Maximum ...

Page 9

AC Parameters ( 3.3V ±5 DDA Symbol Description TPeriod CPU(0:7), (0:7)#) Period Tr/Tf CPU[(0:7), (0:7)#] Rise and Fall Times TSKEW1 Skew from Any CPU Pair to Any CPU Pair TCJJ CPU[(0:7), (0:7)#] Cycle to Cycle ...

Page 10

Sample Layout +3.3V Supply Dale ILB1206 - 300 (300 @ 100 MHz) Cermaic Caps C1 & 10–22 µ VIA to GND plane layer Note: Each supply plane or strip should have a ...

Page 11

... Ordering Information Part Number CY28159PVC CY28159PVCT CY28159ZC CY28159ZCT Package Drawing and Dimensions 48-Lead Shrunk Small Outline Package O48 Document #: 38-07118 Rev. *A Package Type 48-Pin SSOP 48-Pin SSOP - Tape and Reel 48-Pin TSSOP 48-Pin TSSOP - Tape and Reel CY28159 Product Flow Commercial ...

Page 12

... Document #: 38-07118 Rev. *A © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 13

Document Title: CY28159 Clock Generator for Serverworks Grand Champion Chipset Applications Document Number: 38-07118 Issue Orig. of REV. ECN NO. Date Change ** 111426 01/22/02 *A 122789 12/27/02 Document #: 38-07118 Rev. *A Description of Change DMG New data sheet ...

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