CAT24WC16P ON Semiconductor, CAT24WC16P Datasheet

Page 1

... Write Protect Feature — Entire Array Protected When Page Write Buffer DESCRIPTION The CAT24WC01/02/04/08/ 1K/2K/4K/8K/16K- bit Serial CMOS EEPROM internally organized as 128/ 256/512/1024/2048 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces de- vice power requirements. The the CAT24WC01/02/04/ PIN CONFIGURATION ...

Page 2

CAT24WC01/02/04/08/16 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. – +125 C Storage Temperature ....................... – +150 C Voltage on Any Pin with (1) Respect to Ground ........... –2. with Respect to Ground ............... ...

Page 3

A.C. CHARACTERISTICS V = +1.8V to +5.5V, unless otherwise specified. CC Read & Write Cycle Limits ...

Page 4

CAT24WC01/02/04/08/16 FUNCTIONAL DESCRIPTION The CAT24WC01/02/04/08/16 supports the I data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus transmitter and any device receiving data receiver. Data transfer ...

Page 5

CAT24WC01 or CAT24WC02 device. All three address pins are used for these densities. If only one CAT24WC01 or CAT24WC02 is addressed on the bus, all three address pins (A0, A1and A2) can be left floating or connected to ...

Page 6

CAT24WC01/02/04/08/16 Figure 5. Slave Address Bits CAT24WC01/02 CAT24WC04 CAT24WC08 CAT24WC16 * A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device. ** a8, a9 and a10 correspond to the address of the memory array ...

Page 7

Master is allowed to send up to fifteen additional bytes. After each byte has been transmitted the CAT24WC01/02/04/08/16 will respond with an acknowledge, and internally increment the low order address bits by one. The high order bits remain unchanged. ...

Page 8

CAT24WC01/02/04/08/16 Selective Read Selective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte address ...

Page 9

Figure 9. Selective Read Timing BUS ACTIVITY: SLAVE R MASTER ADDRESS T SDA LINE S Figure 10. Sequential Read Timing BUS ACTIVITY: SLAVE MASTER ADDRESS SDA LINE © Catalyst Semiconductor, Inc. Characteristics subject to ...

Page 10

CAT24WC01/02/04/08/16 8-LEAD 300 MIL WIDE PLASTIC DIP (P, L, GL) 0.355 (9.02) 0.400 (10.16) 0.100 (2.54) BSC 0.045 (1.14) 0.060 (1.52) 0.014 (0.36) 0.022 (0.56) Notes: 1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may ...

Page 11

LEAD MSOP (R, Z, GZ) 0.0256 [0.65] BSC 0.0433 [1.10] MAX. 0.1220 0.0276 0.70 0.1142 0.0157 0.40 Notes: (1) All dimensions are in mm Angles in degrees. 2 Does not include Mold Flash, Protrusion or Gate Burrs. Mold Flash, ...

Page 12

CAT24WC01/02/04/08/16 8-LEAD TSSOP (U, Y, GY) Doc. No. 1022, Rev Characteristics subject to change without notice © Catalyst Semiconductor, Inc. ...

Page 13

ORDERING INFORMATION Prefix Device # 24WC02 CAT Product Number Optional 24WC01: 1K Company ID 24WC02: 2K 24WC04: 4K 24WC08: 8K 24WC16: 16K Package P: PDIP J: SOIC, JEDEC U: TSSOP** R: MSOP** L: PDIP (Lead-free, Halogen-free) W: SOIC (Lead-free, Halogen-free) ...

Page 14

REVISION HISTORY Date Rev. 2/3/2004 H Added: CAT24WC01/02/16 not recommended for new designs. See CAT24FC01, CAT24FC02 and CAT24FC16 data sheets 5/28/2004 I Added Die Revision to ordering information 7/28/2004 J Update DC operating characteristics and notes 1/27/2005 K Added Die ...