HD6473297F16 Renesas Electronics America, HD6473297F16 Datasheet
HD6473297F16
Specifications of HD6473297F16
Related parts for HD6473297F16
HD6473297F16 Summary of contents
Page 1
To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
Page 2
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
Page 3
To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
Page 4
Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
Page 5
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. Renesas Single-Chip Microcomputer Hardware Manual H8/3297 Series ...
Page 6
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole ...
Page 7
The H8/3297 Series is a series of high-performance microcontrollers with a fast H8/300 CPU core and a set of on-chip supporting functions optimized for embedded control. These include ROM, RAM, three types of timers, a serial communication interface, A/D converter, ...
Page 8
...
Page 9
Main Revisions and Additions in this Edition Page Item 4 Table 1-1 14 Table 1-3 37, 38 Notes on Bit Manipulation Instructions 69 Figure 4-3 71 Figure 4-4 90 6.2 113 Table 7-9 133 Table 7-15 Port 7 Input Register ...
Page 10
Section 1 Overview 1.1 Overview ........................................................................................................................ 1.2 Block Diagram................................................................................................................ 1.3 Pin Assignments and Functions...................................................................................... 1.3.1 Pin Arrangement............................................................................................. 1.3.2 Pin Functions .................................................................................................. Section 2 CPU ............................................................................................................... 17 2.1 Overview ........................................................................................................................ 17 2.1.1 Features........................................................................................................... 17 2.1.2 Address Space................................................................................................. 18 2.1.3 Register Configuration.................................................................................... ...
Page 11
Section 3 MCU Operating Modes and Address Space 3.1 Overview ........................................................................................................................ 53 3.1.1 Mode Selection ............................................................................................... 53 3.1.2 Mode and System Control Registers ............................................................. 54 3.2 System Control Register (SYSCR)................................................................................. 54 3.3 Mode Control Register (MDCR) .................................................................................... 56 3.4 Address ...
Page 12
Section 7 I/O Ports 7.1 Overview ........................................................................................................................ 91 7.2 Port 1 ........................................................................................................................ 93 7.2.1 Overview......................................................................................................... 93 7.2.2 Register Configuration and Descriptions........................................................ 94 7.2.3 Pin Functions in Each Mode........................................................................... 96 7.2.4 Input Pull-Up Transistors ............................................................................... 98 7.3 Port 2 ........................................................................................................................ 99 ...
Page 13
Timer Interrupt Enable Register (TIER)......................................................... 131 8.2.5 Timer Control/Status Register (TCSR) .......................................................... 133 8.2.6 Timer Control Register (TCR)........................................................................ 135 8.2.7 Timer Output Compare Control Register (TOCR)......................................... 137 8.3 CPU Interface ................................................................................................................. 139 8.4 Operation ........................................................................................................................ 142 8.4.1 FRC Incrementation ...
Page 14
Section 10 Watchdog Timer 10.1 Overview ........................................................................................................................ 181 10.1.1 Features........................................................................................................... 181 10.1.2 Block Diagram................................................................................................ 182 10.1.3 Register Configuration.................................................................................... 182 10.2 Register Descriptions...................................................................................................... 183 10.2.1 Timer Counter (TCNT)................................................................................... 183 10.2.2 Timer Control/Status Register (TCSR) .......................................................... 183 10.2.3 Register Access............................................................................................... 185 10.3 ...
Page 15
Features........................................................................................................... 237 12.1.2 Block Diagram................................................................................................ 238 12.1.3 Input Pins ........................................................................................................ 239 12.1.4 Register Configuration.................................................................................... 240 12.2 Register Descriptions...................................................................................................... 241 12.2.1 A/D Data Registers (ADDRA to ADDRD)........................................ 241 12.2.2 A/D Control/Status Register (ADCSR) .......................................................... 242 12.2.3 A/D ...
Page 16
Exit from Sleep Mode..................................................................................... 269 15.3 Software Standby Mode ................................................................................................. 270 15.3.1 Transition to Software Standby Mode............................................................ 270 15.3.2 Exit from Software Standby Mode ................................................................. 270 15.3.3 Clock Settling Time for Exit from Software Standby Mode.......................... 271 15.3.4 Sample ...
Page 17
Appendix D Pin States D.1 Port States in Each Mode................................................................................................ 371 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix F Product Code Lineup Appendix G Package Dimensions ..................................................................................................... 371 .............................................................. 373 ............................................................................... 374 ................................................................................ 376 ...
Page 18
Overview The H8/3297 Series of single-chip microcomputers features an H8/300 CPU core and a complement of on-chip supporting modules implementing a variety of system functions. The H8/300 CPU is a high-speed processor with an architecture featuring powerful bit-manipulation instructions, ...
Page 19
Table 1-1 Features Item Specification CPU Two-way general register configuration • Eight 16-bit registers, or • Sixteen 8-bit registers High-speed operation • Maximum clock rate ( • 16-bit register-register add/subtract: 125 ns (16 MHz), 167 ns (12 MHz), ...
Page 20
Table 1-1 Features (cont) Item Specification Interrupts • Four external interrupt lines: • 19 on-chip interrupt sources Wait control • Three selectable wait modes Operating • Expanded mode with on-chip ROM disabled (mode 1) modes • Expanded mode with on-chip ...
Page 21
... H8/3297 H8/3296 H8/3294 ZTAT H8/3294 H8/3292 Part Number 5-V Version 3-V Version (16 MHz) (10 MHz) 4-V Version (12 MHz) HD6473297C16 HD6473297C16 HD6473297P16 HD6473297P16 HD6473297F16 HD6473297F16 HD6473297TF16 HD6473297TF16 HD6433297P16 HD6433297VP10 HD6433297P12 HD6433297F16 HD6433297VF10 HD6433297F12 HD6433297TF16 HD6433297VTF10 80-pin TQFP HD6433297TF12 HD6433296P16 HD6433296VP10 HD6433296P12 HD6433296F16 HD6433296VF10 ...
Page 22
Block Diagram Figure 1-1 shows a block diagram of the H8/3297 Series ...
Page 23
Pin Assignments and Functions 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the DC-64S and DP-64S packages. Figure 1-3 shows the pin arrangement of the FP-64A package. Figure 1-4 shows the pin arrangement of the TFP-80C package. ...
Page 24
...
Page 25
...
Page 26
Pin Functions (1) Pin Assignments in Each Operating Mode: Table 1-2 lists the assignments of the pins of the DC-64S, DP-64S, FP-64A, and TFP-80C packages in each operating mode. Table 1-2 Pin Assignments in Each Operating Mode Pin No. ...
Page 27
Table 1-2 Pin Assignments in Each Operating Mode (cont) Pin No. DC-64S DP-64S FP-64A TFP-80C Mode 1 — — ...
Page 28
Table 1-2 Pin Assignments in Each Operating Mode (cont) Pin No. DC-64S DP-64S FP-64A TFP-80C Mode — — — — ...
Page 29
Pin Functions: Table 1-3 gives a concise description of the function of each pin. Table 1-3 Pin Functions DC-64S Type Symbol DP-64S FP-64A TFP-80C Power Clock XTAL 17 EXTAL 18 ø ...
Page 30
Table 1-3 Pin Functions (cont) DC-64S Type Symbol DP-64S FP-64A TFP-80C Data bus 61 WAIT Bus 8 control NMI Interrupt 13 ...
Page 31
Table 1-3 Pin Functions (cont) DC-64S Type Symbol DP-64S FP-64A TFP-80C 16-bit free- FTOA, 32, running FTOB 37 timer (FRT) FTCI 31 FTIA 32, 33, 35, I FTID 8-bit TMO , 35, 0 ...
Page 32
Table 1-3 Pin Functions (cont) DC-64S Type Symbol DP-64S FP-64A TFP-80C General 54 purpose I 44, ...
Page 33
16 ...
Page 34
Overview The H8/300 CPU is a fast central processing unit with eight 16-bit general registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high-speed operation. 2.1.1 Features The main features of the H8/300 CPU ...
Page 35
Address Space The H8/300 CPU supports an address space with a maximum size of 64 kbytes for program code and data combined. The memory map differs depending on the mode (mode 3). For details, see section ...
Page 36
Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as data ...
Page 37
Bit 6—User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 5—Half-Carry Flag (H): This flag is set to 1 when the ADD.B, ADDX.B, SUB.B, SUBX.B, NEG.B, or ...
Page 38
Data Formats The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. • Bit manipulation instructions operate on 1-bit data specified as bit ..., 7) in ...
Page 39
Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-3. Data Type Register No 1-bit data RnH 1-bit data RnL 7 Byte data RnH MSB ...
Page 40
Memory Data Formats Figure 2-4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded ...
Page 41
Addressing Modes 2.4.1 Addressing Mode The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these addressing modes. Table 2-1 Addressing Modes No. Addressing Mode (1) Register direct (2) Register indirect (3) Register indirect with displacement ...
Page 42
Register Indirect with Pre-Decrement—@–Rn The @–Rn mode is used with MOV instructions that store register contents to memory similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction ...
Page 43
Calculation of Effective Address Table 2-2 shows how the H8/300 calculates effective addresses in each addressing mode. Arithmetic, logic, and shift instructions use register direct addressing (1). The ADD.B, ADDX.B, SUBX.B, CMP.B, AND.B, OR.B, and XOR.B instructions can also ...
Page 44
27 ...
Page 45
28 ...
Page 46
29 ...
Page 47
Instruction Set The H8/300 CPU has 57 types of instructions, which are classified by function in table 2-3. Table 2-3 Instruction Classification Function Instructions Data transfer MOV, MOVTPE Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, ...
Page 48
Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats. Table 2-4 Data Transfer Instructions Instruction Size* MOV B/W MOVTPE B MOVFPE B PUSH W POP W Note: * Size: Operand size ...
Page 49
Legend op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2-5 ...
Page 50
Arithmetic Operations Table 2-5 describes the arithmetic instructions. See figure 2-6 in section 2.5.4, Shift Operations, for their object codes. Table 2-5 Arithmetic Instructions Instruction Size* ADD B/W SUB ADDX B SUBX INC B DEC ADDS W SUBS DAA ...
Page 51
Logic Operations Table 2-6 describes the four instructions that perform logic operations. See figure 2-6 in section 2.5.4, Shift Operations, for their object codes. Table 2-6 Logic Operation Instructions Instruction Size* Function AND B Rd Performs a logical AND ...
Page 52
Legend op: Operation field rm, rn: Register field IMM: Immediate data Figure 2-6 Arithmetic, Logic, and Shift Instruction Codes ...
Page 53
Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats. Table 2-8 Bit-Manipulation Instructions Instruction Size* Function BSET B 1 Sets a specified bit in a general register or memory to 1. The bit ...
Page 54
Table 2-8 Bit-Manipulation Instructions (cont) Instruction Size* Function BIXOR B C XORs the C flag with the inverse of a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. BLD B (<bit ...
Page 55
Before Execution of BCLR Instruction Input/output Input Input Pin state Low High DDR Execution of BCLR Instruction BCLR #0, @P1DDR After Execution of BCLR Instruction Input/output Output Output Pin ...
Page 56
Legend op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 ...
Page 57
Branching Instructions Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats. Table 2-9 Branching Instructions Instruction Size Function Bcc — Branches if condition cc is true. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) ...
Page 58
Legend op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2-8 Branching Instruction Codes 8 7 disp 8 ...
Page 59
System Control Instructions Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats. Table 2-10 System Control Instructions Inst5ruction Size Function RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to the ...
Page 60
Block Data Transfer Instruction Table 2-11 describes the EEPMOV instruction. Figure 2-10 shows its object code format. Table 2-11 Block Data Transfer Instruction/EEPROM Write Operation Instruction Si ze Function if R4L ≠ 0 then EEPMOV — else next; Moves ...
Page 61
Notes on EEPMOV Instruction 1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified the address specified by R6 R4L 2. ...
Page 62
CPU States 2.6.1 Overview The CPU has three states: the program execution state, exception-handling state, and power-down state. The power-down state is further divided into three modes: sleep mode, software standby mode, and hardware standby mode. Figure 2-11 summarizes ...
Page 63
Exception handling request Exception- handling state RES = 1 Reset state A transition to the reset state occurs when RES goes low, except when the chip Notes the hardware standby mode. A transition from any state to ...
Page 64
Software Standby Mode: Is entered if the SLEEP instruction is executed while the SSBY (Software Standby) bit in the system control register (SYSCR) is set. The CPU and all on-chip supporting modules halt. The on-chip supporting modules are initialized, ...
Page 65
Internal address bus Internal read signal Internal data bus (read) Internal write signal Internal data bus (write) Figure 2-13 On-Chip Memory Access Cycle ø Address bus AS: High RD: High WR: High Data bus: high impedance state Figure 2-14 ...
Page 66
Access to On-Chip Register Field and External Devices The on-chip supporting module registers and external devices are accessed in a cycle consisting of three states and T . Only one byte of data can be ...
Page 67
Address bus AS: High RD: High WR: High Data bus: high impedance state Figure 2-16 Pin States during On-Chip Register Field Access Cycle ø Address bus AS RD WR: High Data bus Figure 2-17 (a) External Device Access Timing ...
Page 68
T 1 ø Address bus AS RD: High WR Data bus Figure 2-17 (b) External Device Access Timing (Write) Write cycle T state state 2 Address Write data 51 T state 3 ...
Page 69
...
Page 70
Section 3 MCU Operating Modes and Address Space 3.1 Overview 3.1.1 Mode Selection The H8/3297 Series operates in three modes numbered 1, 2, and 3. The mode is selected by the inputs at the mode pins (MD 1 Table 3-1 ...
Page 71
Mode and System Control Registers Table 3-2 lists the registers related to the chip’s operating mode: the system control register (SYSCR) and mode control register (MDCR). The mode control register indicates the inputs to the mode pins MD and ...
Page 72
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. During the selected time the CPU and on-chip ...
Page 73
Bit 1—Reserved: This bit cannot be modified and is always read as 1. Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by a reset, but is not initialized in the software standby mode. ...
Page 74
Address Space Map in Each Operating Mode Figures 3-1 to 3-4 show memory maps of the H8/3297, H8/3296, H8/3294, and H8/3292 in modes 1, 2, and 3. Mode 1 Expanded Mode without On-Chip ROM H'0000 Vector table H'0049 H'004A ...
Page 75
Mode 1 Expanded Mode without On-Chip ROM H'0000 Vector table H'0049 H'004A External address space H'F77F H'F780 *2 On-chip RAM , 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF Notes not access reserved ...
Page 76
Figure 3-3 H8/3294 Address Space Map 59 ...
Page 77
Figure 3-4 H8/3292 Address Space Map 60 ...
Page 78
Section 4 Exception Handling 4.1 Overview The H8/3297 Series recognizes two kinds of exceptions: interrupts and the reset. Table 4-1 indicates their priority and the timing of their hardware exception-handling sequence. Table 4-1 Hardware Exception-Handling Sequences and Priority Type of ...
Page 79
Figure 4-1 indicates the timing of the reset sequence in modes 2 and 3. Figure 4-2 indicates the timing in mode 1. RES/watchdog timer reset (internal) ø Internal address bus Internal read signal Internal write signal Internal data bus (16 ...
Page 80
63 ...
Page 81
Disabling of Interrupts after Reset After a reset interrupt were to be accepted before initialization of the stack pointer (SP: R7), the program counter and condition code register might not be saved correctly, leading to a program ...
Page 82
Table 4-2 Interrupts Interrupt source NMI IRQ0 IRQ1 IRQ2 Reserved 16-bit free- ICIA (Input capture A) running timer ICIB (Input capture B) ICIC (Input capture C) ICID (Input capture D) OCIA (Output compare A) OCIB (Output compare B) FOVI (Overflow) ...
Page 83
Interrupt-Related Registers The interrupt-related registers are the system control register (SYSCR), IRQ sense control register (ISCR), and IRQ enable register (IER). Table 4-3 Registers Read by Interrupt Controller Name System control register IRQ sense control register IRQ enable register ...
Page 84
Bits 2 to 0—IRQ to IRQ Sense Control (IRQ2SC to IRQ0SC): These bits determine whether 2 0 IRQ to IRQ are level-sensed or sensed on the falling edge Bits IRQ2SC to IRQ0SC Description 0 An ...
Page 85
External Interrupts The four external interrupts are NMI and IRQ from software standby mode. (1) NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input signal regardless of whether the I (interrupt mask) ...
Page 86
Interrupt Handling Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt requests, commands the CPU to start the hardware interrupt exception-handling sequence, and furnishes the necessary vector number. Figure 4-3 shows a block diagram of the ...
Page 87
When an NMI or another enabled interrupt is requested, the interrupt controller transfers the interrupt request to the CPU and indicates the corresponding vector number. (When two or more interrupts are requested, the interrupt controller selects the vector number of ...
Page 88
Program execution Interrupt requested? Yes NMI IRQ ? 0 Yes IRQ Yes Latch vector no. Save PC Save CCR Reset I 1 Read vector address Branch to software interrupt-handling routine Figure 4-4 Hardware Interrupt-Handling Sequence 71 ...
Page 89
SP – – – – (R7) Stack area Before interrupt is accepted PC: Program counter CCR: Condition code register SP: Stack pointer Notes: 1. The PC contains the address of the first ...
Page 90
Interrupt accepted Interrupt priority decision. Wait for Instruction end of instruction. prefetch Interrupt request signal ø Internal address (1) bus Internal read signal Internal write signal Internal 16-bit (2) data bus (1) Instruction prefetch address (Pushed on stack. Instruction is ...
Page 91
Interrupt Response Time Table 4-4 indicates the number of states that elapse from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. Since on-chip memory is accessed 16 bits at a time, very ...
Page 92
Precaution Note that the following type of contention can occur in interrupt handling. When software clears the enable bit of an interrupt disable the interrupt, the interrupt becomes disabled after execution of the clearing instruction. If ...
Page 93
Note on Stack Handling In word access, the least significant bit of the address is always assumed The stack is always accessed by word access. Care should be taken to keep an even value in the ...
Page 94
Section 5 Wait-State Controller 5.1 Overview The H8/3297 Series has an on-chip wait-state controller that enables insertion of wait states into bus cycles for interfacing to low-speed external devices. 5.1.1 Features Features of the wait-state controller are listed below. • ...
Page 95
Input/Output Pins Table 5-1 summarizes the wait-state controller’s input pin. Table 5-1 Wait-State Controller Pins Name Abbreviation WAIT Wait 5.1.4 Register Configuration Table 5-2 summarizes the wait-state controller’s register. Table 5-2 Register Configuration Address Name H'FFC2 Wait-state control register ...
Page 96
Bits 7 and 6—Reserved Bit 5—Clock Double (CKDBL): Controls frequency division of clock signals supplied to supporting modules. For details, see section 6, Clock Pulse Generator. Bit 4—Reserved: This bit is reserved, but it can be written and read. Its ...
Page 97
Wait Modes Analog power supply: Analog power supply pin for the A/D converter. If the A/D converter is not used, connect AV to the system power supply (V CC count WC0 = 1). ø ...
Page 98
Pin Wait Mode: In all accesses to external addresses, the number of wait states (T bits WC1 and WC0 are inserted. If the of these wait states, an additional wait state is inserted. If the WAIT pin remains low, wait ...
Page 99
Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (T WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (ø) in the ...
Page 100
Section 6 Clock Pulse Generator 6.1 Overview The H8/3297 Series has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a duty adjustment circuit, and a divider and a prescaler that generates clock signals for the on-chip supporting ...
Page 101
Wait-State Control Register (WSCR) WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals supplied to the supporting modules. It also controls wait-state insertion. WSCR is initialized to H' reset and in hardware ...
Page 102
Oscillator Circuit If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit generates a system clock signal. Alternatively, an external clock signal can be applied to the EXTAL pin. (1) Connecting an External ...
Page 103
Crystal Oscillator: Figure 6-3 shows an equivalent circuit of the crystal resonator. The crystal resonator should have the characteristics listed in table 6-2. XTAL Figure 6-3 Equivalent Circuit of External Crystal Table 6-2 External Crystal Parameters Frequency (MHz ...
Page 104
Note on Board Design: When an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. See figure 6-4. The crystal and its load capacitors should be ...
Page 105
Input of External Clock Signal Circuit Configuration: An external clock signal can be input as shown in the examples in figure 6-5. In example (b) in figure 6-5, the external clock signal should be kept high during standby. If ...
Page 106
External Clock Input The external clock signal should have the same frequency as the desired system clock (ø). Clock timing parameters are given in table 6-3 and figure 6-6. Table 6-3 Clock Timing Item Symbol Low pulse t EXL width ...
Page 107
Table 6.4 shows the external clock output settling delay time, and figure 6.7 shows the external clock output settling delay timing. The oscillator and duty adjustment circuit have the function of adjusting the waveform of the external clock input at ...
Page 108
Overview The H8/3297 Series has five 8-bit input/output ports, one 8-bit input port, and one 3-bit input/output port. Table 7-1 lists the functions of each port in each operating mode. As table 7-1 indicates, the port pins are multiplexed, ...
Page 109
Table 7-1 Port Functions Port Description Pins Port 1 • 8-bit I/O port P1 • Can drive LEDs • Built-in input pull-ups Port 2 • 8-bit I/O port P2 • Can drive LEDs • Built-in input pull-ups Port 3 • ...
Page 110
Port 1 7.2.1 Overview Port 8-bit input/output port with the pin configuration shown in figure 7-1. The pin functions differ depending on the operating mode. Port 1 has built-in, software-controllable MOS input pull-up transistors that can ...
Page 111
Register Configuration and Descriptions Table 7-2 summarizes the port 1 registers. Table 7-2 Port 1 Registers Name Port 1 data direction register Port 1 data register Port 1 input pull-up control register Port 1 Data Direction Register (P1DDR) Bit ...
Page 112
Port 1 Data Register (P1DR) Bit Initial value 0 Read/Write R/W P1DR is an 8-bit register that stores data for pins P1 is read, the value in P1DR is obtained directly, regardless of the actual pin state. ...
Page 113
Pin Functions in Each Mode Port 1 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 1 ...
Page 114
Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 1 can provide lower address output pins and general input pins. Each pin becomes a lower address output pin if its P1DDR bit is set to 1, and ...
Page 115
Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected individually. A pin becomes a general input pin when its P1DDR bit is cleared to 0 and a general output pin when ...
Page 116
Port 2 7.3.1 Overview Port 8-bit input/output port with the pin configuration shown in figure 7-5. The pin functions differ depending on the operating mode. Port 2 has built-in, software-controllable MOS input pull-up transistors that can ...
Page 117
Register Configuration and Descriptions Table 7-4 summarizes the port 2 registers. Table 7-4 Port 2 Registers Name Port 2 data direction register Port 2 data register Port 2 input pull-up control register Port 2 Data Direction Register (P2DDR) Bit ...
Page 118
Port 2 Data Register (P2DR) Bit Initial value 0 Read/Write R/W P2DR is an 8-bit register that stores data for pins P2 is read, the value in P2DR is obtained directly, regardless of the actual pin state. ...
Page 119
Pin Functions in Each Mode Port 2 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 2 ...
Page 120
Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 2 can provide upper address output pins and general input pins. Each pin becomes an upper address output pin if its P2DDR bit is set to 1, and ...
Page 121
Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected individually. A pin becomes a general input pin when its P2DDR bit is cleared to 0, and a general output pin when ...
Page 122
Input Pull-Up Transistors Port 2 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode ...
Page 123
Port 3 7.4.1 Overview Port 8-bit input/output port with the pin configuration shown in Figure 7-9. The pin functions differ depending on the operating mode. Port 3 has built-in, software-controllable MOS input pull-up transistors that can ...
Page 124
Register Configuration and Descriptions Table 7-6 summarizes the port 3 registers. Table 7-6 Port 3 Registers Name Port 3 data direction register Port 3 data register Port 3 input pull-up control register Port 3 Data Direction Register (P3DDR) Bit ...
Page 125
Port 3 Data Register (P3DR) Bit Initial value 0 Read/Write R/W P3DR is an 8-bit register that stores data for pins P3 is read, the value in P3DR is obtained directly, regardless of the actual pin state. ...
Page 126
Pin Functions in Each Mode Port 3 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) ...
Page 127
Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected individually. A pin becomes a general input pin when its P3DDR bit is cleared to 0, and a general output pin when ...
Page 128
Port 4 7.5.1 Overview Port 8-bit input/output port that is multiplexed with interrupt input pins (IRQ input/output pins for bus control signals converter, and an output pin (ø) for the system clock. Figure 7-12 shows the ...
Page 129
Register Configuration and Descriptions Table 7-8 summarizes the port 4 registers. Table 7-8 Port 4 Registers Name Port 4 data direction register Port 4 data register Notes: 1. Bit 6 is read-only. 2. Bit 6 is undetermined. Other bits ...
Page 130
Port 4 Data Register (P4DR) Bit Initial value 0 Read/Write R/W Note: * Determined by the level at pin P4 P4DR is an 8-bit register that stores data for pins P4 is read, the value in P4DR ...
Page 131
Table 7-19 Port 4 Pin Functions (cont) Pin Pin Functions and Selection Method P4 /AS Bit P4 DDR and the operating mode select the pin function as follows 5 5 Operating mode P4 DDR 5 Pin function P4 /WR Bit ...
Page 132
Port 5 7.6.1 Overview Port 3-bit input/output port that is multiplexed with input/output pins (TxD, RxD, SCK) of serial communication interface. The port 5 pin functions are the same in all operating modes. Figure 7-13 shows ...
Page 133
Port 5 Data Direction Register (P5DDR) 7 Bit — Initial value 1 Read/Write — P5DDR is an 8-bit register that controls the input/output direction of each pin in port 5. A pin functions as an output pin if the corresponding ...
Page 134
Pin Functions Port 5 has the same pin functions in each operating mode. All pins can also be used as SCI input/output pins. Table 7-11 indicates the pin functions of port 5. Table 7-11 Port 5 Pin Functions Pin ...
Page 135
Port 6 7.7.1 Overview Port 8-bit input/output port that is multiplexed with input/output pins (FTOA, FTOB, FTIA to FTID, FTCI) of the 16-bit free-running timer (FRT) and with input/output pins (TMRI TMCI , TMCI , TMO ...
Page 136
Register Configuration and Descriptions Table 7-12 summarizes the port 6 registers. Table 7-12 Port 6 Registers Name Port 6 data direction register Port 6 data register Port 6 Data Direction Register (P6DDR) Bit 7 P6 DDR P6 7 Initial ...
Page 137
Port 6 Data Register (P6DR) Bit Initial value 0 Read/Write R/W P6DR is an 8-bit register that stores data for pins P6 is read, the value in P6DR is obtained directly, regardless of the actual pin state. ...
Page 138
Pin Functions Port 6 has the same pin functions all operating modes. The pins are multiplexed with FRT input/output, and 8-bit timer input/output. Table 7-13 indicates the pin functions of port 6. Table 7-13 Port 6 Pin Functions Pin ...
Page 139
Table 7-13 Port 6 Pin Functions (cont) Pin Pin Functions and Selection Method P6 /FTIB/ 3 TMRI P6 DDR 0 3 Pin function TMRI input is usable when bits CCLR1 and CCLR0 are both set TCR of ...
Page 140
Port 7 7.8.1 Overview Port 8-bit input port that also provides the analog input pins for the A/D converter. The pin functions are the same in all modes. Figure 7-15 shows the pin configuration of port ...
Page 141
Register Configuration and Descriptions Table 7-14 summarizes the port 7 registers. Port input port, so there is no data direction register. Table 7-14 Port 7 Register Name Port 7 input register Port 7 Input Register (P7PIN) ...
Page 142
Section 8 16-Bit Free-Running Timer 8.1 Overview The H8/3297 Series has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free- running counter as a time base. Applications of the FRT module include rectangular-wave output (up to two ...
Page 143
Block Diagram Figure 8-1 shows a block diagram of the free-running timer. Internal clock sources ø External clock source ø ø FTCI Clock select Compare- match A FTOA 0 FTOB 0 Compare- match B Control logic FTIA FTIB FTIC ...
Page 144
Input and Output Pins Table 8-1 lists the input and output pins of the free-running timer module. Table 8-1 Input and Output Pins of Free-Running Timer Module Name Abbreviation Counter clock input FTCI Output compare A FTOA Output compare ...
Page 145
Table 8-2 Register Configuration (cont.) Name Input capture register B (high) Input capture register B (low) Input capture register C (high) Input capture register C (low) Input capture register D (high) Input capture register D (low) 8.2 Register Descriptions 8.2.1 ...
Page 146
Output Compare Registers A and B (OCRA and OCRB) Bit Initial value Read/ Write R/W R/W R/W OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually compared with the ...
Page 147
IEDGA Edge detect and capture signal FTIA generating circuit BUFEA: Buffer enable A IEDGA: Input edge select A IEDGC: Input edge select C ICRC: Input capture register C ICRA: Input capture register A FRC: Free-running counter Similarly, when the BUFEB ...
Page 148
Timer Interrupt Enable Register (TIER) Bit 7 ICIAE Initial value 0 Read/Write R/W The TIER is an 8-bit readable/writable register that enables and disables interrupts. The TIER is initialized to H' reset and in the standby modes. ...
Page 149
Bit 4—Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input capture interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1. Bit 4 ICIDE Description 0 Input capture interrupt request D ...
Page 150
Timer Control/Status Register (TCSR) Bit 7 ICFA Initial value 0 Read/Write R/(W)* Note: * Software can write bits clear the flags, but cannot write these bits. TCSR is an ...
Page 151
Bit 5—Input Capture Flag C (ICFC): This status bit is set flag input of a rising or falling edge of FTIC as selected by the IEDGC bit. When BUFEA = 0, this indicates capture of the FRC ...
Page 152
Bit 2—Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value matches the OCRB value. This flag must be cleared by software set by hardware, however, and cannot be set by software. ...
Page 153
Bit 7—Input Edge Select A (IEDGA): This bit selects the rising or falling edge of the input capture A signal (FTIA). Bit 7 IEDGA Description 0 Input capture A events are recognized on the falling edge of FTIA. 1 Input ...
Page 154
Bit 2—Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for ICRB. Bit 2 BUFEB Description 0 ICRD is used for input capture D. 1 ICRD is used as a buffer register for input ...
Page 155
Bit 3—Output Enable A (OEA): This bit enables or disables output of the output compare A signal (FTOA). Bit 3 OEA Description 0 Output compare A output is disabled. 1 Output compare A output is enabled. Bit 2—Output Enable B ...
Page 156
CPU Interface The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture registers (ICRA to ICRD) are 16-bit registers, but they are connected to an 8-bit data bus. When the CPU accesses these registers, to ensure ...
Page 157
Upper byte write CPU writes interface data H'AA (2) Lower byte write CPU writes interface data H'55 Figure 8-3 (a) Write Access to FRC (when CPU Writes H'AA55) Bus FRCH [ ] Bus FRCH [H'AA] 140 Module data bus ...
Page 158
Upper byte read CPU reads interface data H'AA (2) Lower byte read CPU reads interface data H'55 Figure 8-3 (b) Read Access to FRC (when FRC Contains H'AA55) Bus FRCH [H'AA] Bus FRCH [ 141 Module data bus TEMP ...
Page 159
Operation 8.4.1 FRC Incrementation Timing FRC increments on a pulse generated once for each period of the selected (internal or external) clock source. The clock source is selected by bits CKS0 and CKS1 in the TCR. Internal Clock: The ...
Page 160
External Clock: If external clock input is selected, FRC increments on the rising edge of the FTCI clock signal. Figure 8-5 shows the increment timing. The pulse width of the external clock signal must be at least 1.5 system clock ...
Page 161
Output Compare Timing When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 8-6 shows the timing of this operation ...
Page 162
FRC Clear Timing If the CCLRA bit in TCSR is set to 1, the FRC is cleared when compare-match A occurs. Figure 8-7 shows the timing of this operation. ø Internal compare- match A signal FRC Figure 8-7 Clearing ...
Page 163
Input Capture Timing (1) Input Capture Timing: An internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin FTIx ( D), as selected by the ...
Page 164
Buffered Input Capture Timing: ICRC and ICRD can operate as buffers for ICRA and ICRB. Figure 8-10 shows how input capture operates when ICRA and ICRC are used in buffer mode and IEDGA and IEDGC are set to different ...
Page 165
When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by ...
Page 166
Timing of Input Capture Flag (ICF) Setting The input capture flag ICFx ( set the internal input capture signal. Figure 8-12 shows the timing of this operation. ø Internal input ...
Page 167
Setting of Output Compare Flags A and B (OCFA and OCFB) The output compare flags are set internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is ...
Page 168
Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 8-14 shows the timing of this operation. ø FRC Internal overflow signal OVF Figure 8-14 ...
Page 169
Sample Application In the example below, the free-running timer is used to generate two square-wave outputs with a 50% duty cycle and arbitrary phase relationship. The programming is as follows: (1) The CCLRA bit in TCSR is set to ...
Page 170
Usage Notes Application programmers should note that the following types of contention can occur in the free- running timer. (1) Contention between FRC Write and Clear internal counter clear signal is generated during the T state of ...
Page 171
Contention between FRC Write and Increment FRC increment pulse is generated during the T state of a write cycle to the lower byte of the free-running counter, the write takes 3 priority and FRC is not incremented. ...
Page 172
Contention between OCR Write and Compare-Match compare-match occurs during the T state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the 3 compare-match signal is inhibited. Figure 8-18 ...
Page 173
Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as ...
Page 174
Table 8-5 Effect of Changing Internal Clock Sources (cont) No. Description 3 High low: CKS1 and CKS0 are rewritten while old clock source is high and new clock source is low. 4 High high: CKS1 and CKS0 are rewritten while ...
Page 175
...
Page 176
Overview The H8/3297 Series includes an 8-bit timer module with two channels (numbered 0 and 1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value ...
Page 177
Block Diagram Figure 9-1 shows a block diagram of one channel in the 8-bit timer module. Internal External clock sources clock source TMCI Clock select TMO TMRI Control logic Interrupt signals TCR: Timer control register (8 bits) TCSR: Timer ...
Page 178
Input and Output Pins Table 9-1 lists the input and output pins of the 8-bit timer. Table 9-1 Input and Output Pins of 8-Bit Timer Abbreviation* Name Channel 0 Timer output TMO 0 Timer clock input TMCI 0 Timer ...
Page 179
Register Descriptions 9.2.1 Timer Counter (TCNT) Bit 7 Initial value 0 Read/Write R/W Each timer counter (TCNT 8-bit up-counter that increments on a pulse generated from an internal or external clock source selected by clock select bits ...
Page 180
Timer Control Register (TCR) Bit 7 CMIEB CMIEA Initial value 0 Read/Write R/W TCR is an 8-bit readable/writable register that selects the clock source and the time at which the timer counter is cleared, and enables interrupts. TCR is ...
Page 181
Bit 5—Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer overflow interrupt (OVI) when the overflow flag (OVF) in TCSR is set to 1. Bit 5 OVIE Description 0 The timer overflow interrupt request (OVI) is ...
Page 182
Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 and ICKS0 in the serial/timer control register (STCR) select the internal or external clock source for the timer counter. Six internal clock sources, derived by ...
Page 183
Timer Control/Status Register (TCSR) Bit 7 CMFB CMFA Initial value 0 Read/Write R/(W)* R/(W)* Note: * Software can write bits clear the flags, but cannot write these bits. TCSR ...
Page 184
Bit 5—Timer Overflow Flag (OVF): This status flag is set to 1 when the timer count overflows (changes from H'FF to H'00). OVF must be cleared by software set by hardware, however, and cannot be set by software. ...
Page 185
Serial/Timer Control Register (STCR) Bit 7 — Initial value 1 Read/Write — STCR is an 8-bit readable/writable register that controls the operating mode of the serial communication interface, and selects internal clock sources for the timer counters. STCR is ...
Page 186
Operation 9.3.1 TCNT Incrementation Timing The timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source. Internal Clock: Internal clock sources are created from the system clock by a prescaler. ...
Page 187
External Clock: If external clock input (TMCI) is selected, the timer counter can increment on the rising edge, the falling edge, or both edges of the external clock signal. Figure 9-3 shows incrementation on both edges of the external clock ...
Page 188
Compare Match Timing (1) Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are set internal compare-match signal generated when the timer count matches the time constant in TCORA or TCORB. ...
Page 189
Output Timing: When a compare-match event occurs, the timer output changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits, the output can remain the same, change to 0, change to ...
Page 190
External Reset of TCNT When the CCLR1 and CCLR0 bits in TCR are both set to 1, the timer counter is cleared on the rising edge of an external reset input. Figure 9-7 shows the timing of this operation. ...
Page 191
Interrupts Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B (CMIA and CMIB), and overflow (OVI). Each interrupt can be enabled or disabled by an enable bit in TCR. Independent signals are ...
Page 192
Usage Notes Application programmers should note that the following types of contention can occur in the 8-bit timer. 9.6.1 Contention between TCNT Write and Clear If an internal counter clear signal is generated during the T counter, the clear ...
Page 193
Contention between TCNT Write and Increment If a timer counter increment pulse is generated during the T counter, the write takes priority and the timer counter is not incremented. Figure 9-11 shows this type of contention. ø Internal address ...
Page 194
Contention between TCOR Write and Compare-Match If a compare-match occurs during the T and the compare-match signal is inhibited. Figure 9-12 shows this type of contention. ø Internal address bus Internal write signal TCNT TCOR Compare-match ...
Page 195
Contention between Compare-Match A and Compare-Match B If identical time constants are written in TCORA and TCORB, causing compare-match A and B to occur simultaneously, any conflict between the output selections for compare-match A and B is resolved by ...
Page 196
Table 9-5 Effect of Changing Internal Clock Sources No. Description *1 1 Low low *2 2 Low high Notes: 1. Including a transition from low to the stopped state (CKS1 = 0, CKS0 = 0 transition from the ...
Page 197
Table 9-5 Effect of Changing Internal Clock Sources (cont) No. Description *1 3 High low 4 High high Notes: 1. Including a transition from high to the stopped state. 2. The switching of clock sources is regarded as a falling ...
Page 198
Section 10 Watchdog Timer 10.1 Overview The H8/3297 Series has an on-chip watchdog timer (WDT) that can monitor system operation by resetting the CPU or generating a nonmaskable interrupt if a system crash allows the timer count to overflow. When ...
Page 199
Block Diagram Figure 10 block diagram of the watchdog timer. Internal NMI (Watchdog timer mode) Interrupt signals OVF (Interval timer mode) Internal reset TCNT: Timer counter TCSR: Timer control/status register Figure 10-1 Block Diagram of Watchdog Timer ...
Page 200
Register Descriptions 10.2.1 Timer Counter (TCNT) Bit 7 Initial value 0 Read/Write R/W TCNT is an 8-bit readable/writable up-counter. When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts ...