CAT25C256K-TE13 ON Semiconductor, CAT25C256K-TE13 Datasheet
CAT25C256K-TE13
Specifications of CAT25C256K-TE13
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CAT25C256K-TE13 Summary of contents
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Advanced Information CAT25C128/256 128K/256K-Bit SPI Serial CMOS E FEATURES 5 MHz SPI Compatible 1.8 to 6.0 Volt Operation Hardware and Software Protection Zero Standby Current Low Power CMOS Technology SPI Modes (0,0 &1,1) Commercial, Industrial and Automotive Temperature Ranges DESCRIPTION ...
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ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. – +125 C Storage Temperature ....................... – +150 C Voltage on any Pin with (1) Respect to V .................. –2. with Respect ...
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Figure 1. Sychronous Data Timing CSS V IH SCK VALID HI Note: Dashed Line= mode (1, 1) — — ...
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FUNCTIONAL DESCRIPTION The CAT25C128/256 supports the SPI bus data trans- mission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C128/256 to interface directly with many of today’s popular microcontrollers. The CAT25C128/256 contains an 8-bit instruction regis- ter. (The instruction ...
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STATUS REGISTER The Status Register indicates the status of the device. The RDY (Ready) bit indicates whether the CAT25C128/ 256 is busy with a write operation. When set write cycle is in progress and when set to ...
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DEVICE OPERATION Write Enable and Disable The CAT25C128/256 contains a write enable latch. This latch must be set before any write operation. The device powers write disable state when V WREN instruction will enable writes (set the ...
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WRITE Sequence The CAT25C128/256 powers Write Disable state. Prior to any write instructions, the WREN instruc- tion must be sent to CAT25C128/256. The device goes into Write enable state by pulling the CS low and then clocking ...
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During an internal write cycle, all commands will be ignored except the RDSR (Read Status Register) in- struction. The Status Register can be read to determine if the write cycle is still in progress. If Bit 0 of the Status ...
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DESIGN CONSIDERATIONS The CAT25C128/256 powers write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be ...
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Doc. No. 25088-00 8/99 SPI-1 10 ...