M24256-WMW6T STMicroelectronics, M24256-WMW6T Datasheet
M24256-WMW6T
Specifications of M24256-WMW6T
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M24256-WMW6T Summary of contents
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... Kbit, 64 Kbit and 32 Kbit serial I²C bus EEPROM Features 2 ■ Supports the I C bus 100 kHz Standard-mode and 400 kHz Fast-mode ■ Single supply voltages (see part numbers): – 2 5.5 V – 1 5.5 V – 1 5.5 V ■ Write Control input ■ Byte and Page Write ■ ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M24128, M24C64, M24C32 5 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M24128, M24C64, M24C32 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Description 1 Description The M24C32, M24C64 and M24128 devices are I programmable memories (EEPROM). They are organized as 4096 × 8 bits, 8192 × 8 bits and 16384 × 8 bits, respectively. Figure 1. Logic diagram uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I bus definition ...
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M24128, M24C64, M24C32 Table 2. Signal names Signal name E0, E1, E2 SDA SCL Figure 2. DIP, SO, TSSOP and UFDFPN connections 1. See Package mechanical data Figure 3. M24128 WLCSP connections (top view, marking ...
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Signal description 2 Signal description 2.1 Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a ...
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M24128, M24C64, M24C32 2.5 V ground the reference for the V SS 2.6 Supply voltage (V 2.6.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within ...
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Signal description Figure 5. Maximum R 100 Figure bus protocol SCL SDA SCL SDA Start Condition SCL SDA 10/39 value versus bus parasitic capacitance (C) for 100 1000 Bus line ...
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M24128, M24C64, M24C32 Table 3. Device select code Device select code 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. Table 4. Address most ...
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Memory organization 3 Memory organization The memory is organized as shown in Figure 7. Block diagram SCL SDA 12/39 Figure 7. Control Logic I/O Shift Register Address Register and Counter M24128, M24C64, M24C32 High Voltage Generator ...
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M24128, M24C64, M24C32 4 Device operation The device supports the I data on to the bus is defined transmitter, and any device that reads the data receiver. The device that controls the data transfer ...
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Device operation 4.5 Memory addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 3 (on Serial ...
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M24128, M24C64, M24C32 Figure 8. Write mode sequences with (data write inhibited) WC Byte Write WC Page Write WC (cont'd) Page Write (cont'd) ACK ACK Dev select Byte address Byte address R/W ACK ACK Dev select Byte ...
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Device operation 4.6 Write operations Following a Start condition the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in address bytes. The device responds to each address ...
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... The M24128 and M24C64 in UFDFPN8 (MLP) 2 × package and the M24128 in WLCSP package offer an ECC (error correction code) logic which compares each 4-byte word with its six associated EEPROM ECC bits result single bit out of 4 bytes of data happens to be erroneous during a read operation, the ECC detects it and replaces it by the correct value ...
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Device operation Figure 10. Write cycle polling flowchart using ACK First byte of instruction with already decoded by the device 4.10 Minimizing system delays by polling on ACK During the internal Write cycle, the device disconnects itself ...
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M24128, M24C64, M24C32 Figure 11. Read mode sequences Current Address Read Random Address Read Sequential Current Read Sequential Random Read 1. The seven most significant bits of the device select code of a Random Read (in the 1 be identical. ...
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Device operation 4.11 Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device’s internal address counter is incremented by one, to point to the ...
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... These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7. ...
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DC and AC parameters 7 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from ...
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M24128, M24C64, M24C32 Table 12. Input parameters Symbol C Input capacitance (SDA Input capacitance (other pins input impedance WCL ( input impedance WCH Pulse width ignored ( (Input filter on ...
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DC and AC parameters Table 14. DC characteristics (M24xxx-W, device grade 3) Symbol Input leakage current I LI (SCL, SDA, E2, E1, E0) I Output leakage current LO I Supply current (Read Supply current (Write) CC0 I Standby ...
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M24128, M24C64, M24C32 Table 16. DC characteristics (M24xxx-F) Symbol Input leakage current I LI (SCL, SDA, E2, E1, E0) I Output leakage current LO I Supply current (Read Supply current (Write) CC0 I Standby supply current CC1 Input ...
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DC and AC parameters Table 17. AC characteristics (M24xxx-W6, M24xxW3, M24xxR6) Symbol Alt SCL t t CHCL HIGH t t CLCH LOW ( XH1XH2 R ( XL1XL2 DL1DL2 F t ...
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M24128, M24C64, M24C32 Table 18. AC characteristics (M24xxx-F) Symbol Alt SCL t t CHCL HIGH t t CLCH LOW ( XH1XH2 R ( XL1XL2 DL1DL2 DXCX SU:DAT ...
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DC and AC parameters Figure 13. AC waveforms tXL1XL2 tXH1XH2 SCL tDLCL SDA In tCHDX tXH1XH2 Start condition SCL SDA In tCHDH Stop condition SCL tCLQV SDA Out 28/39 tCHCL tCLCH tCLDX tDXCX SDA Change SDA Input tW Write cycle ...
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M24128, M24C64, M24C32 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available ...
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Package mechanical data Figure 15. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline A2 1. Drawing is not to scale. Table 20. SO8 narrow – 8 lead plastic small outline, 150 mils body width, ...
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M24128, M24C64, M24C32 Figure 16. TSSOP8 – 8 lead thin shrink small outline, package outline Drawing is not to scale. Table 21. TSSOP8 – 8 lead thin shrink small outline, package mechanical data Symbol ...
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Package mechanical data Figure 17. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package outline 1. Drawing is not to scale. Table 22. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual ...
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M24128, M24C64, M24C32 Figure 18. M24128 WLCSP, 0.5 mm pitch, package outline Drawing is not to scale. Table 23. M24128 WLCSP, 0.5 mm pitch, package mechanical data Symbol Typ. A 0.585 A1 0.230 A2 0.355 B ...
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... Part numbering 9 Part numbering Table 24. Ordering information scheme Example: Device type 2 M24 = I C serial access EEPROM Device function 128–B = 128 Kbit (16384 x 8) C64– Kbit (8192 x 8) C32– Kbit (4096 x 8) Operating voltage Package BN = PDIP8 ...
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M24128, M24C64, M24C32 Table 25. Available M24C32 products (package, voltage range, temperature grade) Package DIP8 (BN) SO8N (MN) TSSOP8 (DW) MLP8 (MB) Table 26. Available M24C64 products (package, voltage range, temperature grade) Package DIP8 (BN) SO8N (MN) TSSOP8 (DW) MLP8 ...
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Revision history 10 Revision history Table 28. Document revision history Date Revision 22-Dec-1999 28-Jun-2000 31-Oct-2000 20-Apr-2001 16-Jan-2002 02-Aug-2002 04-Feb-2003 27-May-2003 22-Oct-2003 01-Jun-2004 04-Nov-2004 05-Jan-2005 36/39 TSSOP8 package in place of TSSOP14 ( OrderingInfo, 2.3 PackageMechData). 2.4 TSSOP8 package ...
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M24128, M24C64, M24C32 Table 28. Document revision history (continued) Date Revision 29-Jun-2006 03-Jul-2006 17-Oct-2006 27-Apr-2007 27-Nov-2007 Document converted to new ST template. M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed. M24C64 and M24C32 products (1.7 to 5.5V supply ...
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Revision history Table 28. Document revision history (continued) Date Revision 18-Dec-2007 30-May-2008 15-Jul-2008 16-Sep-2008 05-Jan-2009 38/39 Added Section 2.6.2: Power-up Device reset, and Section 2.6.4: Power-down conditions Supply voltage (VCC). Updated Figure 5: Maximum RP value versus bus parasitic capacitance ...
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... M24128, M24C64, M24C32 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...