M69030 Asiliant Technologies, M69030 Datasheet - Page 130

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

9-28
3
2
1
0
Note: The two tables that follow show the possible ways in which the address bits from the memory address
counter can be shifted and/or reorganized before being presented to the frame buffer address decoder.
First, the address bits generated by the memory address counter (MAOut0 to MAOut15) are reorganized,
if needed, to accommodate byte, word, or doubleword modes. The resulting reorganized outputs (Reorg0
to Reorg15) may then also be further manipulated with the substitution of bits from the row scan counter
(RSOut0 and RSOut1) before finally being presented to the input bits of the frame buffer address decoder
(FBIn15-FBIn0).
`efmp

Count By 2
Horizontal Retrace Select
Select Row Scan Counter
Compatibility Mode Support
69030 Databook
0: The memory address counter is incremented either every character clock or every 4
character clocks, depending upon the setting of bit 5 of the Underline Location Register.
1: The memory address counter is incremented either every other clock.
This bit is used in conjunction with bit 5 of the Underline Location Register (CR14) to select
the number of character clocks required to cause the memory address counter to be
incremented as shown, below:
This bit provides a method to effectively double the vertical resolution by allowing the
vertical timing counter to be clocked by the horizontal retrace clock divided by 2 (usually, it
would be undivided).
0: The vertical timing counter is clocked by the horizontal retrace clock.
1: The vertical timing counter is clocked by the horizontal retrace clock divided by 2.
0: A substitution takes place, whereby bit 14 of the 16-bit memory address generated by
the memory address counter (after the stage at which these 16 bits may have already been
shifted to accommodate word or doubleword addressing) is replaced with bit 1 of the row
scan counter at a stage just before this address is presented to the frame buffer address
decoder.
1: No substitution takes place.
See the note at the end of this register description for an overview of the interactions
between this and other bits.
0: A substitution takes place, whereby bit 13 of the 16-bit memory address generated by
the memory address counter (after the stage at which these 16 bits may have already been
shifted to accommodate word or doubleword addressing) is replaced with bit 0 of the row
scan counter at a stage just before this address is presented to the frame buffer address
decoder.
1: No substitution takes place.
See the note at the end of this register description for an overview of the interactions
between this and other bits.
CR14
Bit 5
0
0
1
1
CR17
Bit 3
0
1
0
1
CRT Controller Registers
Address Incrementing Interval
every 2 character clocks
every 4 character clocks
every 2 character clocks
every character clock
Revision 1.3 11/24/99