M69030 Asiliant Technologies, M69030 Datasheet - Page 78
M69030
Manufacturer Part Number
M69030
Description
Manufacturer
Asiliant Technologies
Datasheet
1.M69030.pdf
(387 pages)
Specifications of M69030
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M69030
Manufacturer:
CHIPS
Quantity:
20 000
Part Number:
M69030P
Manufacturer:
MIT
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7-4
5
4
3
2
1
0
`efmp
VGA Palette Snoop
Memory Write & Invalidate
Special Cycles
Bus Master
Memory Access Enable
I/O Access Enable
69030 Databook
0: Accesses to all VGA I/O locations including those for the palette will be claimed. All read
and write accesses to the palette will be performed normally. This is the default after reset.
1: Accesses to all VGA I/O locations, except for those for the palette, will be claimed. All
reads will be entirely ignored, but all writes will still update the palette. This permits
accesses to the palette I/O addresses to be answered by other devices that need to be able
to snoop accesses to the palette.
This bit applies only to PCI Bus masters. Since this graphics controller never functions as
a PCI Bus master, this bit always returns a value of 0 when read.
This graphics controller always ignores all special cycles, therefore this bit always returns
the value of 0 when read.
This graphics controller never functions as a PCI Bus master, therefore this bit always
returns a value of 0 when read.
0: Disables access to the frame buffer memory locations within the range specified by the
MBASE Register. This is the default after reset.
1: Enables access to the frame buffer memory locations within the range specified by the
MBASE Register.
Note:
0: Disables I/O port accesses. This is the default after reset.
1: Enables I/O port accesses.
Note:
Accesses with only adjacent active byte enables are supported.
Accesses with only adjacent active byte enables are supported.
PCI Configuration Registers
Revision 1.3 11/24/99
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