EP2S130F1020I5N Altera, EP2S130F1020I5N Datasheet - Page 153
EP2S130F1020I5N
Manufacturer Part Number
EP2S130F1020I5N
Description
Manufacturer
Altera
Datasheet
1.EP2S130F1020I5N.pdf
(238 pages)
Specifications of EP2S130F1020I5N
Family Name
Stratix II
Number Of Logic Blocks/elements
132540
# I/os (max)
742
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S130F1020I5N
Manufacturer:
ALTERA
Quantity:
215
Part Number:
EP2S130F1020I5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 153 of 238
- Download datasheet (3Mb)
Altera Corporation
April 2011
Low
sustaining
current
High
sustaining
current
Low
overdrive
current
High
overdrive
current
Bus-hold
trip point
25-Ω R
3.3/2.5
Parameter Conditions
Table 5–29. Bus Hold Parameters
Table 5–30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 1 of 2)
Notes (1)
Symbol
S
,
2
Internal series termination with
calibration (25-Ω setting)
Internal series termination without
calibration (25-Ω setting)
V
(maximum)
V
(minimum)
0 V < V
V
0 V < V
V
IN
IN
CCIO
CCIO
> V
< V
IL
IH
IN
IN
<
<
Description
–22.5
22.5
0.45
Min
Bus Hold Specifications
Table 5–29
On-Chip Termination Specifications
Tables 5–30
resistance tolerance when using series or differential on-chip termination.
1.2 V
–120
Max
0.95
120
shows the Stratix II device family bus hold specifications.
and
–25.0
25.0
0.50
Min
1.5 V
V
V
5–31
C C I O
C C I O
–160
Max
1.00
160
Conditions
define the specification for internal termination
= 3.3/2.5 V
= 3.3/2.5 V
–30.0
V
30.0
0.68
Min
CCIO
1.8 V
Level
–200
Max
1.07
200
Stratix II Device Handbook, Volume 1
Commercial
–50.0
50.0
0.70
Min
Max
±30
±5
DC & Switching Characteristics
2.5 V
Resistance Tolerance
–300
Max
1.70
300
Industrial
–70.0
70.0
0.80
Min
Max
±10
±30
3.3 V
–500
Max
2.00
500
Unit
%
%
Unit
5–17
μA
μA
μA
μA
V
Related parts for EP2S130F1020I5N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: