EP2S130F1020I5N Altera, EP2S130F1020I5N Datasheet - Page 60
EP2S130F1020I5N
Manufacturer Part Number
EP2S130F1020I5N
Description
Manufacturer
Altera
Datasheet
1.EP2S130F1020I5N.pdf
(238 pages)
Specifications of EP2S130F1020I5N
Family Name
Stratix II
Number Of Logic Blocks/elements
132540
# I/os (max)
742
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S130F1020I5N
Manufacturer:
ALTERA
Quantity:
215
Part Number:
EP2S130F1020I5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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PLLs & Clock Networks
Figure 2–35. EP2S15 & EP2S30 Device I/O Clock Groups
2–52
Stratix II Device Handbook, Volume 1
IO_CLKH[7:0]
IO_CLKG[7:0]
8
8
8
IOE clocks have row and column block regions that are clocked by eight
I/O clock signals chosen from the 24 quadrant clock resources.
Figures 2–35
regions.
the Quadrant
the Quadrant
24 Clocks in
24 Clocks in
IO_CLKA[7:0]
IO_CLKF[7:0]
and
8
2–36
show the quadrant relationship to the I/O clock
IO_CLKB[7:0]
IO_CLKE[7:0]
8
the Quadrant
the Quadrant
24 Clocks in
24 Clocks in
8
Altera Corporation
8
8
I/O Clock Regions
IO_CLKC[7:0]
IO_CLKD[7:0]
May 2007
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