EP2S130F1020I5N Altera, EP2S130F1020I5N Datasheet - Page 81
EP2S130F1020I5N
Manufacturer Part Number
EP2S130F1020I5N
Description
Manufacturer
Altera
Datasheet
1.EP2S130F1020I5N.pdf
(238 pages)
Specifications of EP2S130F1020I5N
Family Name
Stratix II
Number Of Logic Blocks/elements
132540
# I/os (max)
742
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S130F1020I5N
Manufacturer:
ALTERA
Quantity:
215
Part Number:
EP2S130F1020I5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–48. Column I/O Block Connection to the Interconnect
Note to
(1)
Altera Corporation
May 2007
The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
Figure
Local Interconnect
from Logic Array (1)
Interconnects
R4 & R24
Control Signals
2–48:
I/O Block
32 Data &
Interconnect
LAB
LAB Local
Vertical I/O Block
Interconnects
C4 & C16
32
LAB
Note (1)
IO_dataina[3:0]
IO_datainb[3:0]
Stratix II Device Handbook, Volume 1
LAB
Stratix II Architecture
Vertical I/O
Block Contains
up to Four IOEs
io_clk[7..0]
2–73
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