TE28F640J3D75 Intel, TE28F640J3D75 Datasheet - Page 18

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TE28F640J3D75

Manufacturer Part Number
TE28F640J3D75
Description
Manufacturer
Intel
Datasheet

Specifications of TE28F640J3D75

Cell Type
NOR
Density
64Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Sync/async
Asynchronous
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4Mword
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Table 3:
Datasheet
18
Symbol
D[15:8]
CE[2:0]
BYTE#
VCCQ
VPEN
WE#
GND
CE#
OE#
RP#
STS
VCC
RFU
NC
Signal Descriptions for Numonyx™ Embedded Flash Memory (J3 v. D) (Sheet 2
Open Drain
Output
Output
Supply
of 2)
Input/
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.
Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register
reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode
CHIP ENABLE: Activate the 32-, 64- and 128 Mbit devices’ control logic, input buffers, decoders,
and sense amplifiers. When the device is de-selected, power reduces to standby levels.
All timing specifications are the same for these three signals. Device selection occurs with the first
edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of
CE0, CE1, or CE2 that disables the device.
CHIP ENABLE: Activates the 256Mbit devices’ control logic, input buffers, decoders, and sense
amplifiers.
Device selection occurs with the first edge of CE# that enables the device. Device deselection
occurs with the first edge of CE# that disables the device.s
RESET: RP#-low resets internal automation and puts the device in power-down mode. RP#-high
enables normal operation. Exit from reset sets the device to read array mode. When driven low,
RP# inhibits write operations which provides data protection during power transitions.
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE# is active low.
WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low.
Addresses and data are latched on the rising edge of WE#.
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to
indicate program and/or erase completion. STS is to be tied to VCCQ with a pull-up resistor.
BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0], while
D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-high places
the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the lowest-order
address bit.
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or
configuring lock-bits.
With V
CORE Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when V
≤ V
Caution: Device operation at invalid Vcc voltages should not be attempted.
I/O Power Supply: Power supply for Input/Output buffers.This ball can be tied directly to V
Ground: Ground reference for device logic voltages. Connect to system ground.
No Connect: Lead is not internally connected; it may be driven or floated.
Reserved for Future Use: Balls designated as RFU are reserved by Numonyx for future device
functionality and enhancement.
LKO
PEN
.
≤ V
PENLK
, memory contents cannot be altered.
Name and Function
Numonyx™ Embedded Flash Memory (J3 v. D)
November 2007
308551-05
CC
.
CC

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