TE28F640J3D75 Intel, TE28F640J3D75 Datasheet - Page 34

no-image

TE28F640J3D75

Manufacturer Part Number
TE28F640J3D75
Description
Manufacturer
Intel
Datasheet

Specifications of TE28F640J3D75

Cell Type
NOR
Density
64Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Sync/async
Asynchronous
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4Mword
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
8.3
8.3.1
8.4
Datasheet
34
The CUI does not occupy an addressable memory location. It is written when the device
is enabled and WE# is active. The address and data needed to execute a command are
latched on the rising edge of WE# or the first edge of CE0, CE1, or CE2 that disables
the device (see
Standby
CE0, CE1, and CE2 can disable the device (see
standby mode. This manipulation of CEx substantially reduces device power
consumption. D[15:0] outputs are placed in a high-impedance state independent of
OE#. If deselected during block erase, program, or lock-bit configuration, the WSM
continues functioning, and consuming active power until the operation completes.
Reset/Power-Down
RP# at V
In read modes, RP#-low deselects the memory, places output drivers in a high-
impedance state, and turns off numerous internal circuits. RP# must be held low for a
minimum of t
memory access outputs are valid. After this wake-up interval, normal operation is
restored. The CUI is reset to read array mode and Status Register is set to 0080h.
During Block Erase, Program, or Lock-Bit Configuration modes, RP#-low will abort the
operation. In default mode, STS transitions low and remains low for a maximum time
of t
are no longer valid; the data may be partially corrupted after a program or partially
altered after an erase or lock-bit configuration. Time t
logic-high (V
As with any automated device, it is important to assert RP# during system reset. When
the system comes out of reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed during Block Erase, Program,
or Lock-Bit Configuration modes. If a CPU reset occurs with no flash memory reset,
proper initialization may not occur because the flash memory may be providing status
information instead of array data. Numonyx Flash memories allow proper initialization
following a system reset through the use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets the system CPU.
Device Commands
When the V
identifier codes, or blocks are enabled. Placing V
erase, program, and lock-bit configuration operations. Device operations are selected
by writing specific commands to the Command User Interface (CUI). The CUI does not
occupy an addressable memory location. It is the mechanism through which the flash
device is controlled.
A command sequence is issued in two consecutive write cycles - a Setup command
followed by a Confirm command. However, some commands are single-cycle
commands consisting of a setup command only. Generally, commands that alter the
contents of the flash device, such as Program or Erase, require at least two write cycles
to guard against inadvertent changes to the flash device. Flash commands fall into two
categories: Basic Commands and Extended Commands. Basic commands are
recognized by all Numonyx Flash devices, and are used to perform common flash
operations such as selecting the read mode, programming the array, or erasing blocks.
Extended commands are product-dependant; they are used to perform additional
features such as software block locking.
Numonyx™ Embedded Flash Memory (J3 v. D).
PLPH
+ t
IL
initiates the reset/power-down mode.
PHRH
PEN
IH
PLPH
) before another command can be written.
voltage ≤ V
Table 15 on page
until the reset operation is complete. Memory contents being altered
. Time t
PHQV
PENLK
is required after return from reset mode until initial
, only read operations from the Status Register, CFI,
31). Standard microprocessor write timings are used.
Table 18
Numonyx™ Embedded Flash Memory (J3 v. D)
Table 15 on page
PENH
describes all applicable commands on
on V
PHWL
PEN
is required after RP# goes to
additionally enables block
31) and place it in
November 2007
308551-05

Related parts for TE28F640J3D75