TE28F640J3D75 Intel, TE28F640J3D75 Datasheet - Page 35

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TE28F640J3D75

Manufacturer Part Number
TE28F640J3D75
Description
Manufacturer
Intel
Datasheet

Specifications of TE28F640J3D75

Cell Type
NOR
Density
64Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Sync/async
Asynchronous
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4Mword
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Numonyx™ Embedded Flash Memory (J3 v. D)
Table 18: Command Bus Operations
Notes:
1.
2.
3.
4.
November 2007
308551-05
In case of 256 Mb device (2x128), the command should be issued to the base address of the die
In case of 256 Mb device (2x128), the command sequence must be repeated for each die at its base address
In case of 256 Mb device (2x128), keep the second cycle to the same address. (i.e. Do not toggle A24 for the second
cycle)
In case of 256 Mb device (2x128), the second cycle must be writtne to the Block Address and Offset address to be
programmed
Program Enhanced Configuration Register
Program OTP Register
Clear Status Register
Program STS Configuration Register
Read Array
Read Status Register
Read Identifier Codes (Read Device Information)
CFI Query
Word/Byte Program
Buffered Program
Block Erase
Program/Erase Suspend
Program/Erase Resume
Lock Block
Unlock Block
Command
Register Data
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Block Address
Block Address
Word Address
Address Bus
Setup Write Cycle
1,2
1
1
1
2
2
2
2
2
1
1
1
2
1
2
0040h/
00D0h
0060h
00C0h
0050h
00B8h
0070h
0090h
0098h
0010h
00E8h
0020h
00B0h
0060h
0060h
00FFh
Data
Bus
Device Address
Device Address
Device Address
Device Address
Address Bus
Register Offset
Block Address
Block Address
Register Data
Confirm Write Cycle
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3
4
Register Data
Register Data
Array Data
Data Bus
00D0h
00D0h
00D0h
0004h
0001h
Datasheet
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