TE28F640J3D75 Intel, TE28F640J3D75 Datasheet - Page 36

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TE28F640J3D75

Manufacturer Part Number
TE28F640J3D75
Description
Manufacturer
Intel
Datasheet

Specifications of TE28F640J3D75

Cell Type
NOR
Density
64Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Sync/async
Asynchronous
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4Mword
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
9.0
9.1
Table 19: Status Register Bit Definitions
Datasheet
36
Status Register (SR)
Status
Ready
Bit
7
7
6
5
4
3
2
1
0
Ready Status
Erase Suspend Status
Erase Error
Program
Error
Program Suspend Status
Block-Locked Error
Error
Suspend
Status
Erase
Flash Operations
This section describes the operational features of flash memory. Operations are
command-based, wherein command codes are first issued to the device, then the
device performs the desired operation. All command codes are issued to the device
using bus-write cycles. A complete list of available command codes can be found in
Section 10.0, “Device Command Codes” on page
Status Register
The Status Register (SR) is an 8-bit, read-only register that indicates device status and
operation errors. To read the Status Register, issue the Read Status Register command.
Subsequent reads output Status Register information on DQ[7:0], and 00h on
DQ[15:8].
SR status bits are set and cleared by the device. SR error bits are set by the device, but
must be cleared using the Clear Status Register command. Upon power-up or exit from
reset, the Status Register defaults to 80h. Page-mode reads are not supported in this
read mode. Status Register contents are latched on the falling edge of OE# or the first
edge of CEx that enables the device. OE# must toggle to V
disabled before further reads to update the Status Register latch. The Read Status
Register command functions independently of V
6
Name
Command
Sequence
Error
Erase
Error
5
0 = Device is busy; SR[6:] are invalid (Not driven);
1 = Device is ready; SR[6:0] are valid.
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
0 =
1 =
aborted.
0 = Program suspend not in effect.
1 = Program suspend in effect.
0 = Block NOT locked during program or erase - operation successful.
1 = Block locked during program or erase - operation aborted.
Program
Error
SR5 SR4
0
0
1
1
4
within acceptable limits during program or erase operation.
not within acceptable limits during program or erase operation. Operation
0
1
0
1
= Program or erase operation successful.
= Program error - operation aborted.
= Erase error - operation aborted.
= Command sequence error - command aborted.
Program/
Voltage
Erase
Error
3
Program
Suspend
Numonyx™ Embedded Flash Memory (J3 v. D)
Status
PEN
Description
47.
2
voltage.
IH
Block-Locked
or the device must be
Error
1
Default Value = 80h
November 2007
308551-05
0

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