TE28F640J3D75 Intel, TE28F640J3D75 Datasheet - Page 37

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TE28F640J3D75

Manufacturer Part Number
TE28F640J3D75
Description
Manufacturer
Intel
Datasheet

Specifications of TE28F640J3D75

Cell Type
NOR
Density
64Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Sync/async
Asynchronous
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4Mword
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Numonyx™ Embedded Flash Memory (J3 v. D)
9.1.1
Table 20: Clear Status Register Command Bus-Cycle
Note:
9.2
Table 21: Read Mode Command Bus-Cycles
9.2.1
November 2007
308551-05
Clear Status Register
Read Array
Read Status Register
Read Device Information
CFI Query
Command
Clearing the Status Register
The Status Register (SR) contain status and error bits which are set by the device. SR
status bits are cleared by the device, however SR error bits are cleared by issuing the
Clear Status Register command. Resetting the device also clears the Status Register.
In case of 256 Mb device (2x128), the command sequence must be repeated for each die at its base address.
Issuing the Clear Status Register command places the device in Read Status Register
mode.
Care should be taken to avoid Status Register ambiguity. If a command sequence error
occurs while in an Erase Suspend condition, the Status Register will indicate a
Command Sequence error by setting SR4 and SR5. When the erase operation is
resumed (and finishes), any errors that may have occurred during the erase operation
will be masked by the Command Sequence error. To avoid this situation, clear the
Status Register prior to resuming a suspended erase operation. The Clear Status
Register command functions independent of the voltage level on VPEN.
Read Operations
Four types of data can be read from the device: array data, device information, CFI
data, and device status. Upon power-up or return from reset, the device defaults to Read Array mode.
To change the device’s read mode, the appropriate command must be issued to the device.
the command codes used to configure the device for the desired read mode. The
following sections describe each read mode.
In case of 256 Mb device (2x128), the command sequence must be repeated for each die at its base address.
Read Array
Upon power-up or return from reset, the device defaults to Read Array mode. Issuing the Read Array
command places the device in Read Array mode. Subsequent reads output array data
on DQ[15:0]. The device remains in Read Array mode until a different read command is
issued, or a program or erase operation is performed, in which case, the read mode is
automatically changed to Read Status.
Command
Device Address
Address Bus
Setup Write Cycle
Device Address
Device Address
Device Address
Device Address
Address Bus
Setup Write Cycle
Data Bus
0050h
Data Bus
0070h
0090h
0098h
00FFh
Address Bus
Address Bus
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Confirm Write Cycle
Confirm Write Cycle
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Table 21
Data Bus
Data Bus
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Datasheet
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37

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