TE28F640J3D75 Intel, TE28F640J3D75 Datasheet - Page 43

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TE28F640J3D75

Manufacturer Part Number
TE28F640J3D75
Description
Manufacturer
Intel
Datasheet

Specifications of TE28F640J3D75

Cell Type
NOR
Density
64Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Sync/async
Asynchronous
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4Mword
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Numonyx™ Embedded Flash Memory (J3 v. D)
Note:
Table 26: STS Configuration Coding Definitions
9.7
9.7.1
Table 27: Block Locking Command Bus-Cycles
Notes:
1.
2.
November 2007
308551-05
00 = default, level mode; device
ready indication
01 = pulse on Erase Complete
10 = pulse on Program Complete
11 = pulse on Erase or Program
Complete
Notes:
1.
2.
3.
Set Block Lock Bit
Clear Block Lock Bits
D[1:0] = STS Configuration
D7
In case of 256 Mb device (2x128), the command should be issued to the base address of the die
In case of 256 Mb device (2x128), the command sequence must be repeated for each die at its base address
When configured in one of the pulse modes, STS pulses low with a typical pulse width of 500 ns.
An invalid configuration code will result in both SR4 and SR5 being set.
Reserved bits are invalid should be ignored.
Codes
D6
The Configuration command may only be given when the device is not busy or
suspended. Check SR.7 for device status. An invalid configuration code will result in
SR.4 and SR.5 being set.
STS Pulse mode is not supported in the Clear Lock Bits and Set Lock Bit commands.
Security and Protection
Numonyx™ Embedded Flash Memory (J3 v. D) device offer both hardware and software
security features. Block lock operations, PRs and VPEN allow users to implement
various levels of data protection.
Normal Block Locking
Numonyx™ Embedded Flash Memory (J3 v. D) has the unique capability of Flexible
Block Locking (locked blocks remain locked upon reset or power cycle): All blocks are
unlocked at the factory. Blocks can be locked individually by issuing the Set Block Lock
Bit command sequence to any address within a block. Once locked, blocks remain
locked when power is removed, or when the device is reset.
All locked blocks are unlocked simultaneously by issuing the Clear Block Lock Bits
command sequence to any device address. Locked blocks cannot be erased or
programmed.
Command
D5
Table 27
Controls HOLD to a memory controller to prevent accessing a flash memory subsystem
while any flash device's WSM is busy.
Generates a system interrupt pulse when any flash device in an array has completed a
block erase. Helpful for reformatting blocks after file system free space reclamation or
“cleanup.”
Not supported on this device.
Generates system interrupts to trigger servicing of flash arrays when either erase or
program operations are completed, when a common interrupt service routine is desired.
Reserved
D4
summarizes the command bus-cycles.
Device Address
Block Address
Address Bus
Setup Write Cycle
D3
1
2
Data Bus
0060h
0060h
Notes
D2
Device Address
Block Address
Address Bus
Complete (1)
Program
Pulse on
Confirm Write Cycle
D1
Pulse on Erase
Complete (1)
Data Bus
00D0h
0001h
D0
Datasheet
43

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