TE28F640J3D75 Intel, TE28F640J3D75 Datasheet - Page 53

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TE28F640J3D75

Manufacturer Part Number
TE28F640J3D75
Description
Manufacturer
Intel
Datasheet

Specifications of TE28F640J3D75

Cell Type
NOR
Density
64Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Sync/async
Asynchronous
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4Mword
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Numonyx™ Embedded Flash Memory (J3 v. D)
Figure 25: Block Erase Flowchart
November 2007
308551-05
Issue Single Block Erase
Command 20H, Block
Write Confirm D0H
Block(s) Complete
Check if Desired
Status Register
Block Address
Erase Flash
Full Status
Address
SR.7 =
Read
Start
1
0
Suspend Erase
No
Yes
1. The Erase Confirm byte must follow Erase Setup.
This device does not support erase queuing. Please see
Application note AP-646 For software erase queuing
compatibility.
Full status check can be done after all erase and write
sequences complete. Write FFH after the last operation to
reset the device to read array mode.
Erase Loop
Write (Note 1)
Suspend
Operation
Standby
Write
Read
Bus
Erase Block
Command
Confirm
Erase
Data = 20H
Addr = Block Address
Data = D0H
Addr = Block Address
Status register data
With the device enabled,
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
OE# low updates SR
Comments
Datasheet
53

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