TE28F640J3D75 Intel, TE28F640J3D75 Datasheet - Page 56

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TE28F640J3D75

Manufacturer Part Number
TE28F640J3D75
Description
Manufacturer
Intel
Datasheet

Specifications of TE28F640J3D75

Cell Type
NOR
Density
64Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Sync/async
Asynchronous
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4Mword
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Figure 28: Clear Lock-Bit Flowchart
Datasheet
56
FULL STATUS CHECK PROCEDURE
Read Status Register
Clear Block Lock-Bits
Read Status Register
Clear Block Lock-Bits
Data (See Above)
Check if Desired
Successful
Full Status
Write D0H
Write 60H
Complete
SR.4,5 =
SR.7 =
SR.3 =
SR.5 =
Start
0
0
0
1
0
1
1
1
Clear Block Lock-Bits
Command Sequence
Voltage Range Error
Error
Error
Write FFH after the clear lock-bits operation to place device in read
array mode.
SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register
command.
If an error is detected, clear the status register before attempting retry
or other error recovery.
Operation
Operation
Standby
Standby
Standby
Standby
Read
Write
Write
Bus
Bus
Numonyx™ Embedded Flash Memory (J3 v. D)
Lock-Bits Confirm
Command
Lock-Bits Setup
Clear Block or
Clear Block
Command
Check SR.3
1 = Programming Voltage Error
Check SR.4, 5
Both 1 = Command Sequence
Check SR.5
1 = Clear Block Lock-Bits Error
Error
Detect
Data = 60H
Addr = X
Data = D0H
Addr = X
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Comments
Comments
November 2007
308551-05

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