TE28F640J3D75 Intel, TE28F640J3D75 Datasheet - Page 64

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TE28F640J3D75

Manufacturer Part Number
TE28F640J3D75
Description
Manufacturer
Intel
Datasheet

Specifications of TE28F640J3D75

Cell Type
NOR
Density
64Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Sync/async
Asynchronous
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4Mword
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Table 41: Protection Register Information
Table 42: Burst Read Information
Table 43: Additional CFI link for the lower die of the stacked device (256 Mb only)
Datasheet
64
Note:
1.
Note:
1.
(P+17)h
(P+18)h
Offset
Offset
Offset
P = 31h
P = 31h
(P+10)h
(P+11)h
(P+12)h
(P+13)h
(P+14)h
(P+15)h
P = 31h
(P+15)h
(P+16)h
(P+E)h
(P+F)h
(1)
(1)
(1)
The variable P is a pointer which is defined at CFI offset 15h.
The variable P is a pointer which is defined at CFI offset 15h.
4
Length
Length
Length
The following table is the extended CFI used for the lower die of 256 Mb (2x128)
device.
1
4
1
1
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection bytes are available
Protection Field 1: Protection Description
This field describes user-available One Time Programmable (OTP)
protection register bytes. Some are pre-programmed with device-
unique serial numbers. Others are user-programmable. Bits 0-15 point
to the protection register lock byte, the section’s first byte. The
following bytes are factory pre-programmed and user-programmable.
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bits 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = “n” such that 2
bits 24-31 = “n” such that 2
Page Mode Read capability
bits 0–7 = “n” such that 2
page bytes. See offset 28h for device word width to determine page-
mode data output width. 00h indicates no read page buffer.
Number of synchronous mode read configuration fields that follow. 00h
indicates no burst capability.
Reserved for future use
Link Field Bit Information
Bits[9:0] = Address offset (within 32 Mbit segment) of reference
CFI table
Bits [27:10] = n
Bits [30:28] = Memory type:
bit 31 = Another CFI link field immediately follows
• 000b = CSD Flash
• 100b = LD Flash
(Optional Flash Features and Commands)
(Optional Flash Features and Commands)
(Optional Flash Features and Commands)
th
32 Mbit segment of referenced CFI table
n
HEX value represents the number of read-
Description
n
n
Description
Description
= factory pre-programmed bytes
= user-programmable bytes
Numonyx™ Embedded Flash Memory (J3 v. D)
46:
47:
48:
49:
bit [9:0] = 10h
bits[27:10] = 04h
bits[30:28] = 0h
Bit 31 = 0h
Add.
Add.
Add.
40:
41:
42:
43:
3F:
44:
45:
46:
Hex Code
--10
--10
--00
--00
Code
Code
Hex
--01
--80
--00
--03
--03
Hex
--03
--00
November 2007
308551-05
10
0
No
4
8bytes
8bytes
Value
Value
8 byte
Value
80h
00h
01
0

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