TC55V8512J-12 Toshiba, TC55V8512J-12 Datasheet

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TC55V8512J-12

Manufacturer Part Number
TC55V8512J-12
Description
Manufacturer
Toshiba
Datasheet

Specifications of TC55V8512J-12

Density
4Mb
Access Time (max)
12ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
19b
Package Type
SOJ
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
170mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
36
Word Size
8b
Number Of Words
512K
Lead Free Status / Rohs Status
Not Compliant
524,288-WORD BY 8-BIT CMOS STATIC RAM
DESCRIPTION
words by 8 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it
operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode,
and output enable ( OE ) provides fast memory access. This device is well suited to cache memory applications
where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL
compatible. The TC55V8512J/FT is available in plastic 36-pin SOJ and 44-pin TSOP with 400mil width for high
density surface assembly.
FEATURES
PIN ASSIGNMENT
GND
I/O1
I/O2
I/O3
I/O4
A17
A16
A15
A14
A13
A18
WE
V
The TC55V8512J/FT is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 524,288
CE
A3
A2
A1
A0
DD
Fast access time (the following are maximum values)
Low-power dissipation
(the following are maximum values)
36 PIN SOJ
Operation (max)
(TC55V8512J)
TC55V8512J/FT-12:12 ns
TC55V8512J/FT-15:15 ns
Standby:4 mA (both devices)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Cycle Time
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
170
12
NC
A4
A5
A6
A7
OE
I/O8
I/O7
GND
V
I/O6
I/O5
A8
A9
A10
A11
A12
NU
DD
(TOP VIEW)
140
15
GND
I/O1
I/O2
I/O3
I/O4
A17
A16
A15
A14
A13
A18
WE
V
NC
NC
CE
NC
NC
44 PIN TSOP
A3
A2
A1
A0
DD
130
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
110
25
(TC55V8512FT)
mA
ns
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A4
A5
A6
A7
OE
I/O8
I/O7
GND
V
I/O6
I/O5
A8
A9
A10
A11
A12
NU
NC
NC
DD
Single power supply voltage of 3.3 V ± 0.3 V
Fully static operation
All inputs and outputs are LVTTL compatible
Output buffer control using OE
Package:
SOJ36-P-400-1.27 (J)
TSOP II44-P-400-0.80 (FT)
PIN NAMES
I/O1 to I/O8
A0 to A18
GND
V
WE
CE
OE
NC
NU
DD
TC55V8512J/FT-12,-15
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power (+3.3 V)
Ground
No Connection
Not Usable (Input)
2001-12-19 1/10
(Weight: 1.35 g typ)
(Weight: 0.45 g typ)

Related parts for TC55V8512J-12

TC55V8512J-12 Summary of contents

Page 1

... OE ) provides fast memory access. This device is well suited to cache memory applications where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL compatible. The TC55V8512J/FT is available in plastic 36-pin SOJ and 44-pin TSOP with 400mil width for high density surface assembly. ...

Page 2

... COLUMN DECODER COLUMN ADDRESS BUFFER CLOCK A10 A11A13 CE RATING min (4 ns max) RC min (4 ns max 0° to 70°C) PARAMETER min (4 ns max) RC min (4 ns max) RC TC55V8512J/FT-12,- GND CE A18 VALUE −0.5 to 4.6 −0.5* to 4.6 −0. 0.5** DD 1.4 260 −65 to 150 − ...

Page 3

... Other Input = − 0.2 V, Other Input = V − TEST CONDITION = GND GND V I TC55V8512J/FT-12,-15 MIN TYP MAX −1  1 −1  1 −1  20 −1  1   2.4 − 0.2     0.4   0   t 170 cycle = 15 ns  ...

Page 4

... TC55V8512J/FT -12 -15 MAX MIN MAX   15      4   4   1   TC55V8512J/FT -12 -15 MAX MIN MAX   15   9   12   12   0   0   8   0   1  ...

Page 5

... Note 6) t OEE (See Note 6) t COE INDETERMINATE (See Note (See Note 6) t ODW (See Note 3) INDETERMINATE TC55V8512J/FT-12,- (See Note 6) t COD (See Note 6) t ODO VALID DATA OUT INDETERMINATE t WR (See Note 6) t OEW Hi-Z (See Note 4) INDETERMINATE VALID DATA IN ...

Page 6

... WRITE CYCLE CONTROLLED) Address Hi-Z OUT D IN (See Note (See Note 6) t ODW (See Note 6) t COE INDETERMINATE t DS VALID DATA IN TC55V8512J/FT-12,- Hi 2001-12-19 6/10 ...

Page 7

... Output Disable Time ・・・・・・・・・・・・・・・・ (A) 0.2 V VALID DATA OUT 0.2 V INDETERMINATE TC55V8512J/FT-12,-15 (B) 0.2 V Hi-Z 0.2 V INDETERMINATE 2001-12-19 7/10 ...

Page 8

... PACKAGE DIMENSIONS Weight: 1.35 g (typ) TC55V8512J/FT-12,-15 2001-12-19 8/10 ...

Page 9

... PACKAGE DIMENSIONS Weight: 0.45 g (typ) TC55V8512J/FT-12,-15 2001-12-19 9/10 ...

Page 10

... TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. TC55V8512J/FT-12,-15 000707EBA 2001-12-19 10/10 ...

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