DSP56301PW80B1 Freescale Semiconductor, DSP56301PW80B1 Datasheet - Page 111

• Manufacturer Part Number: DSP56301PW80B1
• Manufacturer: Freescale Semiconductor

Specifications of DSP56301PW80B1

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
YDAT_END
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ioequ
;------------------------------------------------------------------------
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;------------------------------------------------------------------------
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M_DATH EQU $FFFFCF ; Host port GPIO data Register
M_DIRH EQU $FFFFCE; Host port GPIO direction Register
M_PCRC EQU $FFFFBF; Port C Control Register
M_PRRC EQU $FFFFBE; Port C Direction Register
M_PDRC EQU $FFFFBD ; Port C GPIO Data Register
M_PCRD EQU $FFFFAF ; Port D Control register
M_PRRD EQU $FFFFAE ; Port D Direction Data Register
M_PDRD EQU $FFFFAD; Port D GPIO Data Register
M_PCRE EQU $FFFF9F; Port E Control register
M_PRRE EQU $FFFF9E; Port E Direction Register
M_PDRE EQU $FFFF9D; Port E Data Register
M_OGDB EQU $FFFFFC; OnCE GDB Register
;------------------------------------------------------------------------
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M_DTXS EQU $FFFFCD ; DSP SLAVE TRANSMIT DATA FIFO (DTXS)
M_DTXM EQU $FFFFCC; DSP MASTER TRANSMIT DATA FIFO (DTXM)
M_DRXR EQU $FFFFCB; DSP RECEIVE DATA FIFO (DRXR)
M_DPSR EQU $FFFFCA; DSP PCI STATUS REGISTER (DPSR)
Register Addresses
EQUATES for Host Interface
dc
dc
EQUATES for DSP56301 I/O registers and ports
Reference: DSP56301 Specifications Revision 3.00
Last update:
December 19 1993 (cosmetic - page and opt directives)
August
page
opt
ident
EQUATES for I/O Port Programming
Register Addresses
Changes:
$6162BC
$E4A245
132,55,0,0,0
mex
1,0
9 1994 ESSI and SCI control registers bit update
November 15 1993
GPIO for ports C,D and E,
HI32
DMA status reg
AAR
SCI registers address
SSI registers addr. + split TSR from SSISR
PLL control reg
DSP56301 Technical Data, Rev. 10
A-5