DSP56301PW80B1 Freescale Semiconductor, DSP56301PW80B1 Datasheet - Page 122

• Manufacturer Part Number: DSP56301PW80B1
• Manufacturer: Freescale Semiconductor

Specifications of DSP56301PW80B1

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Power Consumption Benchmark
;
A-16
M_WRP EQU 19
M_SEN EQU 20
;*************************************************************************
;
;
;
;
;
;
;
;
;*************************************************************************
intequ ident
I_VEC
;------------------------------------------------------------------------
; Non-Maskable interrupts
;------------------------------------------------------------------------
I_RESET EQU I_VEC+$00
I_STACK EQU I_VEC+$02
I_ILL
I_DBG
I_TRAP
I_NMI
;------------------------------------------------------------------------
; Interrupt Request Pins
;------------------------------------------------------------------------
I_IRQA
I_IRQB
I_IRQC
I_IRQD
;------------------------------------------------------------------------
; DMA Interrupts
;------------------------------------------------------------------------
I_DMA0
I_DMA1
I_DMA2
I_DMA3
I_DMA4
I_DMA5
;------------------------------------------------------------------------
; Timer Interrupts
;------------------------------------------------------------------------
I_TIM0C EQU I_VEC+$24
I_TIM0OF EQU I_VEC+$26
EQUATES for DSP56301 interrupts
Reference: DSP56301 Specifications Revision 3.00
Last update: November 15 1993 (Debug request & HI32 interrupts)
page
opt
if
;leave user definition as is.
else
equ
endif
EQU I_VEC+$04
EQU I_VEC+$06
EQU I_VEC+$08
EQU I_VEC+$0A
EQU I_VEC+$10
EQU I_VEC+$12
EQU I_VEC+$14
EQU I_VEC+$16
EQU I_VEC+$18
EQU I_VEC+$1A
EQU I_VEC+$1C
EQU I_VEC+$1E
EQU I_VEC+$20
EQU I_VEC+$22
August 16 1994 (change interrupt addresses to be
132,55,0,0,0
mex
@DEF(I_VEC)
$0
1,0
; Extended WRaP flag in OMR.
; Stack Extension Enable bit in OMR.
December 19 1993 (cosmetic - page and opt directives)
relative to I_VEC)
; Hardware RESET
; Stack Error
; Illegal Instruction
; Debug Request
; Trap
; Non Maskable Interrupt
; IRQA
; IRQB
; IRQC
; IRQD
; DMA Channel 0
; DMA Channel 1
; DMA Channel 2
; DMA Channel 3
; DMA Channel 4
; DMA Channel 5
; TIMER 0 compare
; TIMER 0 overflow
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor