DSP56301PW80B1 Freescale Semiconductor, DSP56301PW80B1 Datasheet - Page 17

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DSP56301PW80B1

Manufacturer Part Number
DSP56301PW80B1
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of DSP56301PW80B1

Device Core Size
24b
Format
Fixed Point
Clock Freq (max)
80MHz
Mips
80
Device Input Clock Speed
80MHz
Ram Size
24KB
Program Memory Size
Not RequiredKB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant
Freescale Semiconductor
HPAR
HDAK
HPERR
HDRQ
HGNT
HAEN
HREQ
HTA
Signal Name
Input/
Output
Input
Input/
Output
Output
Input
Input
Output
Output
Type
Tri-stated
Tri-stated
Input
Tri-stated
State During
Table 1-11.
Reset
DSP56301 Technical Data, Rev. 10
Host Parity
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, this is the Host Parity signal.
Host DMA Acknowledge
When HI32 is programmed to interface with a universal, non-PCI bus and the
HI function is selected, this is the Host DMA Acknowledge Schmitt-trigger
signal.
Port B
When the HI32 is configured as GPIO through the DCTR, this signal is
internally disconnected.
This input is 5 V tolerant.
Host Parity Error
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, this is the Host Parity Error signal.
Host DMA Request
When HI32 is programmed to interface with a universal, non-PCI bus and the
HI function is selected, this is the Host DMA Request output.
Port B
When the HI32 is configured as GPIO through the DCTR, this signal is
internally disconnected.
This input is 5 V tolerant.
Host Bus Grant
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, this is the Host Bus Grant signal.
Host Address Enable
When HI32 is programmed to interface with a universal, non-PCI bus and the
HI function is selected, this is the Host Address Enable output signal.
Port B
When the HI32 is configured as GPIO through the DCTR, this signal is
internally disconnected.
This input is 5 V tolerant.
Host Bus Request
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, this is the Host Bus Request signal.
Host Transfer Acknowledge—When HI32 is programmed to interface with a
universal, non-PCI bus and the HI function is selected, this is the Host Data
Bus Enable signal. HTA can be programmed as active high or active low.
Port B
When the HI32 is configured as GPIO through the DCTR, this signal is
internally disconnected.
This input is 5 V tolerant.
Host Interface (Continued)
Signal Description
Host Interface (HI32)
1-13

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