DSP56301PW80B1 Freescale Semiconductor, DSP56301PW80B1 Datasheet - Page 32

• Manufacturer Part Number: DSP56301PW80B1
• Manufacturer: Freescale Semiconductor

Specifications of DSP56301PW80B1

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Specifications
2.5.3
2-6
1
2
3
4
5
6
7
Notes:
Voltage Controlled Oscillator (VCO) frequency when PLL
enabled (MF × E
PLL external capacitor (PCAP pin to V
•
•
Note:
No.
@ MF ≤ 4
@ MF > 4
Frequency of EXTAL (EXTAL Pin Frequency)
The rise and fall time of this external clock should be 3 ns maximum.
EXTAL input high
•
•
EXTAL input low
•
•
EXTAL cycle time
•
•
CLKOUT change from EXTAL fall with PLL disabled
a. CLKOUT rising edge from EXTAL rising edge with PLL enabled (MF
= 1 or 2 or 4, PDF = 1, Ef > 15 MHz)
b. CLKOUT falling edge from EXTAL falling edge with PLL enabled (MF
≤ 4, PDF ≠ 1, Ef / PDF > 15 MHz)
Instruction cycle time = I
(see Table 2-4) (46.7%–53.3% duty cycle)
•
•
1.
2.
3.
4.
5.
6.
C
can be computed from one of the following equations:
With PLL disabled (46.7%–53.3% duty cycle
With PLL enabled (42.5%–57.5% duty cycle
With PLL disabled (46.7%–53.3% duty cycle
With PLL enabled (42.5%–57.5% duty cycle
With PLL disabled
With PLL enabled
With PLL disabled
With PLL enabled
PCAP
Phase Lock Loop (PLL) Characteristics
Measured at 50 percent of the input transition
The maximum value for PLL enabled is given for minimum VCO frequency (see Table 2-6) and maximum MF.
Periodically sampled and not 100 percent tested
The maximum value for PLL enabled is given for minimum VCO frequency and maximum DF.
The skew is not guaranteed for any other MF value.
The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time
required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock
frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time
requirements are met.
(680 × MF) – 120, for MF ≤ 4, or
1100 × MF, for MF > 4.
f
is the value of the PLL capacitor (connected between the PCAP pin and V
× 2/PDF)
Characteristics
1, 2
1, 2
2
CYC
Characteristics
= T
CCP
C
4
3,5
) (C
3,5
PCAP
Table 2-6.
DSP56301 Technical Data, Rev. 10
)
Table 2-5.
6
6
6
6
)
)
)
)
(MF × 580) −
MF × 830
Min
100
PLL Characteristics
30
Clock Operation
80 MHz
(MF × 780) −
MF × 1470
Symbol
Max
ET
ET
I
ET
160
140
CYC
Ef
H
C
L
CCP
12.50 ns
12.50 ns
12.50 ns
5.84 ns
5.31 ns
5.84 ns
5.31 ns
25.0 ns
4.3 ns
0.0 ns
0.0 ns
). The recommended value in pF for C
Min
(MF × 580) − 100
0
MF × 830
80 MHz
Min
30
80.0 MHz
157.0 μs
157.0 μs
273.1 μs
11.0 ns
8.53 μs
1.8 ns
1.8 ns
Max
100 MHz
∞
∞
∞
∞
Freescale Semiconductor
(MF × 780) − 140
10.00 ns
10.00 ns
10.00 ns
4.67 ns
4.25 ns
4.67 ns
4.25 ns
20.0 ns
MF × 1470
4.3 ns
0.0 ns
0.0 ns
Min
Max
0
200
100 MHz
100.0 MHz
157.0 μs
157.0 μs
273.1 μs
11.0 ns
8.53 μs
1.8 ns
1.8 ns
Max
PCAP
∞
∞
∞
∞
Unit
MHz
pF
pF