ISP1761BE STEricsson, ISP1761BE Datasheet - Page 113

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ISP1761BE

Manufacturer Part Number
ISP1761BE
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1761BE

Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
LQFP
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed

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NXP Semiconductors
Table 114. Data Port register (address 0220h) bit description
Table 115. Data Port register (address 0220h) bit description
ISP1761_5
Product data sheet
Bit
31 to 0
Bit
15 to 0
Symbol
DATAPORT
[31:0]
Symbol
DATAPORT
[15:0]
10.6.3 Data Port register
10.6.4 Buffer Length register
This register provides direct access for a microcontroller to the FIFO of the indexed
endpoint.
Peripheral to host (IN endpoint): After each write, an internal counter is automatically
incremented, by two in 16-bit mode and four in 32-bit mode, to the next location in the TX
FIFO. When all bytes have been written (FIFO byte count = endpoint MaxPacketSize), the
buffer is automatically validated. The data packet will then be sent on the next IN token.
Whenever required, the Control Function register (bit VENDP) can validate the endpoint
whose byte count is less than MaxPacketSize.
Remark: The buffer can automatically be validated using the Buffer Length register.
Host to peripheral (OUT endpoint): After each read, an internal counter is automatically
decremented, by two in 16-bit mode and four in 32-bit mode, to the next location in the RX
FIFO. When all bytes have been read, the buffer contents are automatically cleared. A
new data packet can then be received on the next OUT token. Buffer contents can also be
cleared through the Control Function register (bit CLBUF), whenever it is necessary to
forcefully clear contents.
The Data Port register description when the ISP1761 is in 32-bit mode is given in
Table
Access
R/W
The Data Port register description when the ISP1761 is in 16-bit mode is given in
Table
This register determines the current packet size (DATACOUNT) of the indexed endpoint
FIFO. The bit description is given in
The Buffer Length register is automatically loaded with the FIFO size, when the Endpoint
MaxPacketSize register is written (see
required. After a bus reset, the Buffer Length register is made zero.
IN endpoint: When the data transfer is performed in multiples of MaxPacketSize, the
Buffer Length register is not significant. This register is useful only when transferring data
that is not a multiple of MaxPacketSize. The following two examples demonstrate the
significance of the Buffer Length register.
Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register need not be filled. This is because the
transfer size is a multiple of MaxPacketSize, and MaxPacketSize packets will be
automatically validated because the last packet is also of MaxPacketSize.
Access
R/W
114.
115.
Value
0000 0000h
Value
0000 0000h
Rev. 05 — 13 March 2008
Description
Data Port: A 500 ns delay starting from the reception of the endpoint
interrupt may be required for the first read from the data port.
Description
Data Port: A 500 ns delay starting from the reception of the endpoint
interrupt may be required for the first read from the data port.
Table
Table
116.
120). A smaller value can be written when
Hi-Speed USB OTG controller
© NXP B.V. 2008. All rights reserved.
ISP1761
112 of 163

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