ISP1761BE STEricsson, ISP1761BE Datasheet - Page 124

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 141. DcInterrupt - Device Controller Interrupt register (address 0218h) bit allocation
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
10.8.1 DcInterrupt register
10.8 General registers
EP6TX
EP2TX
R/W
R/W
R/W
31
23
15
0
0
0
0
0
0
Table 140. DMA Burst Counter register (address 0264h) bit description
The DcInterrupt register consists of 4 bytes. The bit allocation is given in
When a bit is set in the DcInterrupt register, it indicates that the hardware condition for an
interrupt has occurred. When the DcInterrupt register content is non-zero, the INT output
will be asserted. On detecting the interrupt, the external microprocessor must read the
DcInterrupt register to determine the source of the interrupt.
Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various
bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset.
The DMA controller has only one interrupt bit: the source for a DMA interrupt is shown in
the DMA Interrupt Reason register.
Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can
be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt
Reason register and writing logic 1 to the DMA bit of the DcInterrupt register.
Bit
15 to 13
12 to 0
EP6RX
EP2RX
R/W
R/W
R/W
30
22
14
0
0
0
0
0
0
Symbol
-
BURST
COUNTER[12:0]
EP5TX
EP1TX
R/W
R/W
R/W
29
21
13
0
0
0
0
0
0
reserved
Rev. 05 — 13 March 2008
Description
reserved
Burst Counter: This register defines the burst length. The counter
must be programmed to be a multiple of two in 16-bit mode and four
in 32-bit mode.
The value of the burst counter must be programmed so that the
buffer counter is a factor of the burst counter. In 16-bit mode, DREQ
will drop at every DMA read or write cycle when the burst counter
equals 2. In 32-bit mode, DREQ will drop at every DMA read or
write cycle when the burst counter equals 4.
EP5RX
EP1RX
[1]
R/W
R/W
R/W
28
20
12
0
0
0
0
0
0
EP4TX
EP0TX
R/W
R/W
R/W
27
19
11
0
0
0
0
0
0
EP4RX
EP0RX
R/W
R/W
R/W
26
18
10
0
0
0
0
0
0
Hi-Speed USB OTG controller
reserved
EP7TX
EP3TX
R/W
R/W
R/W
25
17
9
0
0
0
0
0
0
© NXP B.V. 2008. All rights reserved.
ISP1761
Table
[1]
EP0SETUP
141.
EP7RX
EP3RX
123 of 163
R/W
R/W
R/W
24
16
8
0
0
0
0
0
0