ISP1761BE STEricsson, ISP1761BE Datasheet - Page 157

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. HCIVERSION - Host Controller Interface Version
Table 11. HCSPARAMS - Host Controller Structural
Table 12. HCSPARAMS - Host Controller Structural
Table 13. HCCPARAMS - Host Controller Capability
Table 14. HCCPARAMS - Host Controller Capability
Table 15. USBCMD - USB Command register (address
Table 16. USBCMD - USB Command register (address
Table 17. USBSTS - USB Status register (address 0024h)
Table 18. USBSTS - USB Status register (address 0024h)
Table 19. FRINDEX - Frame Index register (address:
Table 20. FRINDEX - Frame Index register (address:
Table 21. CONFIGFLAG - Configure Flag register (address
Table 22. CONFIGFLAG - Configure Flag register (address
Table 23. PORTSC1 - Port Status and Control 1 register
Table 24. PORTSC1 - Port Status and Control 1 register
Table 25. ISO PTD Done Map register (address 0130h) bit
ISP1761_5
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7
Port connection scenarios . . . . . . . . . . . . . . . .16
Memory address . . . . . . . . . . . . . . . . . . . . . . .18
Using the IRQ Mask AND or IRQ Mask OR
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . .28
Pin status during hybrid mode . . . . . . . . . . . . .29
Host controller-specific register overview . . . .32
CAPLENGTH - Capability Length register
(address 0000h) bit description . . . . . . . . . . . .33
Number register (address 0002h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Parameters register (address 0004h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Parameters register (address 0004h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Parameters register (address 0008h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Parameters register (address 0008h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
0020h) bit allocation . . . . . . . . . . . . . . . . . . . . .36
0020h) bit description . . . . . . . . . . . . . . . . . . .36
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .36
bit description . . . . . . . . . . . . . . . . . . . . . . . . .37
002Ch) bit allocation . . . . . . . . . . . . . . . . . . . .37
002Ch) bit description . . . . . . . . . . . . . . . . . . .38
0060h) bit allocation . . . . . . . . . . . . . . . . . . . . .38
0060h) bit description . . . . . . . . . . . . . . . . . . .39
(address 0064h) bit allocation . . . . . . . . . . . . .39
(address 0064h) bit description . . . . . . . . . . . .40
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Rev. 05 — 13 March 2008
Table 26. ISO PTD Skip Map register (address 0134h) bit
Table 27. ISO PTD Last PTD register (address 0138h) bit
Table 28. INT PTD Done Map register (address 0140h) bit
Table 29. INT PTD Skip Map register (address 0144h) bit
Table 30. INT PTD Last PTD register (address 0148h) bit
Table 31. ATL PTD Done Map register (address 0150h) bit
Table 32. ATL PTD Skip Map register (address 0154h) bit
Table 33. ATL PTD Last PTD register (address 0158h) bit
Table 34. HW Mode Control - Hardware Mode Control
Table 35. HW Mode Control - Hardware Mode Control
Table 36. HcChipID - Host Controller Chip Identifier register
Table 37. HcScratch - Host Controller Scratch register
Table 38. SW Reset - Software Reset register (address
Table 39. SW Reset - Software Reset register (address
Table 40. HcDMAConfiguration - Host Controller Direct
Table 41. HcDMAConfiguration - Host Controller Direct
Table 42. HcBufferStatus - Host Controller Buffer Status
Table 43. HcBufferStatus - Host Controller Buffer Status
Table 44. ATL Done Timeout register (address 0338h) bit
Table 45. Memory register (address 033Ch) bit
Table 46. Memory register (address 033Ch) bit
Table 47. Edge Interrupt Count register (address 0340h) bit
Table 48. Edge Interrupt Count register (address 0340h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
register (address 0300h) bit allocation . . . . . . 43
register (address 0300h) bit description . . . . . 44
(address 0304h) bit description . . . . . . . . . . . . 45
(address 0308h) bit description . . . . . . . . . . . . 45
030Ch) bit allocation . . . . . . . . . . . . . . . . . . . . 45
030Ch) bit description . . . . . . . . . . . . . . . . . . . 46
Memory Access Configuration register (address
0330h) bit allocation . . . . . . . . . . . . . . . . . . . . 46
Memory Access Configuration register (address
0330h) bit description . . . . . . . . . . . . . . . . . . . 47
register (address 0334h) bit allocation . . . . . . 47
register (address 0334h) bit description . . . . . 48
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Hi-Speed USB OTG controller
© NXP B.V. 2008. All rights reserved.
ISP1761
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