ISP1761BE STEricsson, ISP1761BE Datasheet - Page 158

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 49. DMA Start Address register (address 0344h) bit
Table 50. DMA Start Address register (address 0344h) bit
Table 51. Power Down Control register (address 0354h) bit
Table 52. Power Down Control register (address 0354h) bit
Table 53. HcInterrupt - Host Controller Interrupt register
Table 54. HcInterrupt - Host Controller Interrupt register
Table 55. HcInterruptEnable - Host Controller Interrupt
Table 56. HcInterruptEnable - Host Controller Interrupt
Table 57. ISO IRQ Mask OR register (address 0318h) bit
Table 58. INT IRQ Mask OR register (address 031Ch) bit
Table 59. ATL IRQ Mask OR register (address 0320h) bit
Table 60. ISO IRQ Mask AND register (address 0324h) bit
Table 61. INT IRQ MASK AND register (address 0328h) bit
Table 62. ATL IRQ MASK AND register (address 032Ch) bit
Table 63. High-speed bulk IN and OUT: bit allocation . . .61
Table 64. High-speed bulk IN and OUT: bit description .62
Table 65. High-speed isochronous IN and OUT: bit
Table 66. High-speed isochronous IN and OUT: bit
Table 67. High-speed interrupt IN and OUT: bit
Table 68. High-speed interrupt IN and OUT: bit
Table 69. Microframe description . . . . . . . . . . . . . . . . . .72
Table 70. Start and complete split for bulk: bit allocation 73
Table 71. Start and complete split for bulk: bit
Table 72. SE description . . . . . . . . . . . . . . . . . . . . . . . . .76
Table 73. Start and complete split for isochronous: bit
Table 74. Start and complete split for isochronous: bit
Table 75. Start and complete split for interrupt: bit
ISP1761_5
Product data sheet
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
(address 0310h) bit allocation . . . . . . . . . . . . .53
(address 0310h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Enable register (address 0314h) bit allocation 55
Enable register (address 0314h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Rev. 05 — 13 March 2008
Table 76. Start and complete split for interrupt: bit
Table 77. Microframe description . . . . . . . . . . . . . . . . . . 84
Table 78. SE description . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 79. OTG controller-specific register overview . . . . 91
Table 80. Address mapping of registers: 32-bit data bus
Table 81. Address mapping of registers: 16-bit data bus
Table 82. Vendor ID - Vendor Identifier (address 0370h)
Table 83. Product ID - Product Identifier register (address
Table 84. OTG Control register (address set: 0374h, clear:
Table 85. OTG Control register (address set: 0374h, clear:
Table 86. OTG Status register (address 0378h) bit
Table 87. OTG Status register (address 0378h) bit
Table 88. OTG Interrupt Latch register (address set: 037Ch,
Table 89. OTG Interrupt Latch register (address set: 037Ch,
Table 90. OTG Interrupt Enable Fall register (address set:
Table 91. OTG Interrupt Enable Fall register (address set:
Table 92. OTG Interrupt Enable Rise register (address set:
Table 93. OTG Interrupt Enable Rise register (address set:
Table 94. OTG Timer register (address low word set: 0388h,
Table 95. OTG Timer register (address low word set: 0388h,
Table 96. Endpoint access and programmability . . . . . 101
Table 97. Peripheral controller-specific register
Table 98. Address register (address 0200h) bit
Table 99. Address register (address 0200h) bit
Table 100.Mode register (address 020Ch) bit allocation 105
Table 101.Mode register (address 020Ch) bit
Table 102.Interrupt Configuration register (address 0210h)
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
register: bit description . . . . . . . . . . . . . . . . . . 92
0372h) bit description . . . . . . . . . . . . . . . . . . . 92
0376h) bit allocation . . . . . . . . . . . . . . . . . . . . 93
0376h) bit description . . . . . . . . . . . . . . . . . . . 93
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
clear: 037Eh) bit allocation . . . . . . . . . . . . . . . 95
clear: 037Eh) bit description . . . . . . . . . . . . . . 95
0380h, clear: 0382h) bit allocation . . . . . . . . . 96
0380h, clear: 0382h) bit description . . . . . . . . 96
0384h, clear: 0386h) bit allocation . . . . . . . . . 96
0384h, clear: 0386h) bit description . . . . . . . . 97
low word clear: 038Ah; high word set: 038Ch, high
word clear: 038Eh) bit allocation . . . . . . . . . . . 97
low word clear: 038Ah; high word set: 038Ch, high
word clear: 038Eh) bit description . . . . . . . . . . 98
overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . 106
Hi-Speed USB OTG controller
© NXP B.V. 2008. All rights reserved.
ISP1761
continued >>
157 of 163