ISP1761BE STEricsson, ISP1761BE Datasheet - Page 25

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
ISP1761_5
Product data sheet
7.5 Phase-Locked Loop (PLL) clock multiplier
With the help of the IRQ Mask AND and IRQ Mask OR registers for each type of transfer
(ISO, INT and bulk), software can determine which PTDs get priority and an interrupt will
be generated when the AND or OR conditions are met. The PTDs that are set will wait
until the respective bits of the remaining PTDs are set and then all PTDs generate an
interrupt request to the CPU together.
The registers definition shows that the AND or OR conditions are applicable to the same
category of PTDs: ISO, INT and ATL.
When an IRQ is generated, the PTD Done Map registers and the respective V bits will
show which PTDs were completed.
The rules that apply to the IRQ Mask AND or IRQ Mask OR settings are:
For an example on using the IRQ Mask AND or IRQ Mask OR registers, without the ATL
Done Timeout register, see
The AND function: activate the IRQ only if PTDs 1, 2 and 4 are done.
The OR function: if any of the PTDs 7, 8 or 9 are done, an IRQ for each of the PTD will be
raised.
Table 5.
The internal PLL requires a 12 MHz input, which can be a 12 MHz crystal or a 12 MHz
clock already existing in the system with a precision better than 50 ppm. This allows the
use of a low-cost 12 MHz crystal that also minimizes ElectroMagnetic Interference (EMI).
When an external crystal is used, make sure the CLKIN pin is connected to V
PTD
1
2
3
4
5
6
7
8
9
•
•
•
The OR mask has a higher priority over the AND mask. An IRQ is generated if bit n of
done map is set and the corresponding bit n of the OR mask register is set.
If the OR mask for any done bit is not set, then the AND mask comes into picture. An
IRQ is generated if all the corresponding done bits of the AND Mask register are set.
For example: If bits 2, 4 and 10 are set in the AND Mask register, an IRQ is generated
only if bits 2, 4, 10 of the done map are set.
If using the IRQ interval setting for the bulk PTD, an interrupt will only occur at the
regular time interval as programmed in the ATL Done Timeout register. Even if an
interrupt event occurs before the time-out of the register, no IRQ will be generated
until the time is up.
AND register
1
1
0
1
0
0
0
0
0
Using the IRQ Mask AND or IRQ Mask OR registers
Rev. 05 — 13 March 2008
OR register
0
0
0
0
0
0
1
1
1
Table
5.
Time
1 ms
-
-
3 ms
-
-
5 ms
6 ms
7 ms
PTD done
1
1
-
1
-
-
1
1
1
Hi-Speed USB OTG controller
IRQ
-
-
-
active because of AND
-
-
active because of OR
active because of OR
active because of OR
© NXP B.V. 2008. All rights reserved.
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CC(I/O)
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