ISP1761BE STEricsson, ISP1761BE Datasheet - Page 38

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
[1]
Table 19.
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
FRINDEX - Frame Index register (address: 002Ch) bit allocation
8.2.3 USBINTR register
8.2.4 FRINDEX register
R/W
R/W
R/W
R/W
23
15
31
0
0
7
0
0
Table 18.
[1]
The USB Interrupt (USBINTR) register is a read or write register located at 0028h. All the
bits in this register are reserved.
The Frame Index (FRINDEX) register is used by the host controller to index into the
periodic frame list. The register updates every 125 s (once each microframe). Bits n to 3
are used to select a particular entry in the periodic frame list during periodic schedule
execution. The number of bits used for the index depends on the size of the frame list as
set by the system software in the FLS (Frame List Size) field of the USBCMD register.
This register must be written as a double word. A word-only write (16-bit mode) produces
undefined results. A write to this register while the RS (Run/Stop) bit is set produces
undefined results. Writes to this register also affect the SOF value. The bit allocation is
given in
Bit
31 to 4
3
2
1 to 0
For details on register bit description, refer to
Universal Serial Bus Rev.
R/W
R/W
R/W
R/W
22
14
30
0
0
6
0
0
Table
Symbol Description
-
FLR
PCD
-
reserved
USBSTS - USB Status register (address 0024h) bit description
19.
[1]
reserved; write logic 0
Frame List Rollover: The host controller sets this bit to logic 1 when the
frame list index rolls over from its maximum value to zero.
Port Change Detect: The host controller sets this bit to logic 1 when any port,
where the PO bit is cleared, has a change to a one or a FPR bit changes to a
one as a result of a J-K transition detected on a suspended port.
reserved
R/W
R/W
R/W
R/W
21
13
29
0
0
5
0
0
Rev. 05 — 13 March 2008
1.0”.
[1]
R/W
R/W
R/W
R/W
20
12
28
0
0
4
0
0
reserved
reserved
reserved
Ref. 2 “Enhanced Host Controller Interface Specification for
[1]
[1]
[1]
R/W
R/W
R/W
R/W
FLR
19
11
27
0
0
3
0
0
PCD
R/W
R/W
R/W
R/W
18
10
26
0
0
2
0
0
Hi-Speed USB OTG controller
R/W
R/W
R/W
R/W
17
25
0
9
0
1
0
0
© NXP B.V. 2008. All rights reserved.
reserved
ISP1761
[1]
R/W
R/W
R/W
R/W
37 of 163
16
24
0
8
0
0
0
0