ISP1761BE STEricsson, ISP1761BE Datasheet - Page 48

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
[1]
Table 42.
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
HcBufferStatus - Host Controller Buffer Status register (address 0334h) bit allocation
8.3.6 HcBufferStatus register
R/W
R/W
31
23
0
0
Table 41.
The HcBufferStatus register is used to indicate the HC that a particular PTD buffer (that is,
ATL, INT and ISO) contains at least one PTD that must be scheduled. Once software sets
the Buffer Filled bit of a particular transfer in the HcBufferStatus register, the HC will start
traversing through PTD headers that are not marked for skipping and are valid PTDs.
Remark: Software can set these bits during the initialization.
Table 42
Bit
31 to 8 DMA_COUNTER[23:0] DMA Counter: The number of bytes to be transferred (read or
7 to 4
3 to 2
1
0
R/W
R/W
30
22
0
0
Symbol
-
BURST_LEN[1:0]
ENABLE_DMA
DMA_READ_WRITE_
SEL
shows the bit allocation of the HcBufferStatus register.
HcDMAConfiguration - Host Controller Direct Memory Access Configuration
register (address 0330h) bit description
R/W
R/W
29
21
0
0
Rev. 05 — 13 March 2008
Description
write).
Remark: Different number of bursts will be generated for the
same transfer length programmed in 16-bit and 32-bit modes
because DMA_COUNTER is in number of bytes.
reserved
DMA Burst Length:
00 — Single DMA burst
01 — 4-cycle DMA burst
10 — 8-cycle DMA burst
11 — 16-cycle DMA burst
Enable DMA:
0 — Terminate DMA
1 — Enable DMA
DMA Read or Write Select: Indicates if the DMA operation is a
write or read to or from the ISP1761.
0 — DMA write to the ISP1761 internal RAM is set
1 — DMA read from the ISP1761 internal RAM
R/W
R/W
28
20
0
0
reserved
reserved
[1]
[1]
R/W
R/W
27
19
0
0
R/W
R/W
26
18
0
0
Hi-Speed USB OTG controller
R/W
R/W
25
17
0
0
© NXP B.V. 2008. All rights reserved.
ISP1761
R/W
R/W
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24
16
0
0