ISP1761BE STEricsson, ISP1761BE Datasheet - Page 55

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
[1]
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
INT_IRQ
R/W
7
0
Table 54.
Bit
31 to 11 -
10
9
8
7
6
READY
CLK
R/W
6
0
Symbol
OTG_IRQ
ISO_IRQ
ATL_IRQ
INT_IRQ
CLKREADY
HcInterrupt - Host Controller Interrupt register (address 0310h) bit
description
HCSUSP
R/W
5
0
Rev. 05 — 13 March 2008
Description
reserved; write reset value
OTG_IRQ: Indicates that an OTG event occurred. The IRQ line will be
asserted if the respective enable bit in the HcInterruptEnable register is
set.
0 — No OTG event
1 — OTG event occurred
For details, see
ISO IRQ: Indicates that an ISO PTD was completed, or the PTDs
corresponding to the bits set in the ISO IRQ Mask AND or ISO IRQ
Mask OR register bits combination were completed. The IRQ line will be
asserted if the respective enable bit in the HcInterruptEnable register is
set.
0 — No ISO PTD event occurred
1 — ISO PTD event occurred
For details, see
ATL IRQ: Indicates that an ATL PTD was completed, or the PTDs
corresponding to the bits set in the ATL IRQ Mask AND or ATL IRQ
Mask OR register bits combination were completed. The IRQ line will be
asserted if the respective enable bit in the HcInterruptEnable register is
set.
0 — No ATL PTD event occurred
1 — ATL PTD event occurred
For details, see
INT IRQ: Indicates that an INT PTD was completed, or the PTDs
corresponding to the bits set in the INT IRQ Mask AND or INT IRQ
Mask OR register bits combination were completed. The IRQ line will be
asserted if the respective enable bit in the HcInterruptEnable register is
set.
0 — No INT PTD event occurred
1 — INT PTD event occurred
For details, see
Clock Ready: Indicates that internal clock signals are running stable.
The IRQ line will be asserted if the respective enable bit in the
HcInterruptEnable register is set.
0 — No CLKREADY event has occurred
1 — CLKREADY event occurred
reserved
R/W
4
0
[1]
Section
Section
Section
Section
DMAEOT
R/W
INT
3
0
7.4.
7.4.
7.4.
7.4.
reserved
R/W
2
0
Hi-Speed USB OTG controller
[1]
SOFITLINT
R/W
1
0
© NXP B.V. 2008. All rights reserved.
ISP1761
reserved
R/W
54 of 163
0
0
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